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- #include "dm9k.h"
- #include "lwip_dm9k.h"
- #include "Lwip_init.h"
- #define Max_Int_Count 1
- #define Broadcast_Jump
- #define Max_Broadcast_Lenth 500
- #define Max_Send_Pack 2
- #define Fix_Note_Address
- uint8_t SendPackOk = 0;
- uint8_t s_FSMC_Init_Ok = 0;
- #define printk myprintf
- void dm9k_debug_test(void);
- void dm9k_udelay(uint16_t time);
- static void dm9k_fsmc(void);
- void dm9k_udelay(uint16_t time)
- {
- us_delay(time);
- }
- uint8_t dm9k_ReadReg(uint8_t reg)
- {
- NET_REG_ADDR = reg;
- return (NET_REG_DATA);
- }
- void dm9k_WriteReg(uint8_t reg, uint8_t writedata)
- {
- NET_REG_ADDR = reg;
- NET_REG_DATA = writedata;
- }
- void dm9k_hash_table(uint8_t *MacAdd)
- {
- uint8_t i;
-
- for (i = 0; i < 6; i++)
- dm9k_WriteReg(DM9K_REG_PAR + i, MacAdd[i]);
- for (i = 0; i < 8; i++)
- dm9k_WriteReg(DM9K_REG_MAR + i, 0xff);
- }
- void dm9k_reset(void)
- {
- dm9k_WriteReg(DM9K_REG_NCR, DM9K_REG_RESET);
- dm9k_udelay(10);
- dm9k_WriteReg(DM9K_REG_NCR, DM9K_REG_RESET);
- dm9k_udelay(10);
-
- dm9k_WriteReg(DM9K_REG_IMR, DM9K_IMR_OFF);
- dm9k_WriteReg(DM9K_REG_TCR2, DM9K_TCR2_SET);
-
- dm9k_WriteReg(DM9K_REG_NSR, 0x2c);
- dm9k_WriteReg(DM9K_REG_TCR, 0x00);
- dm9k_WriteReg(DM9K_REG_ISR, 0x3f);
- #ifdef DM9KA_FLOW_CONTROL
- dm9k_WriteReg(DM9K_REG_BPTR, DM9K_BPTR_SET);
- dm9k_WriteReg(DM9K_REG_FCTR, DM9K_FCTR_SET);
- dm9k_WriteReg(DM9K_REG_FCR, DM9K_FCR_SET);
- #endif
- #ifdef DM9KA_UPTO_100M
-
- dm9k_WriteReg(DM9K_REG_OTCR, DM9K_OTCR_SET);
- #endif
- #ifdef Rx_Int_enable
- dm9k_WriteReg(DM9K_REG_IMR, DM9K_IMR_SET);
- #else
- dm9k_WriteReg(DM9K_REG_IMR, DM9K_IMR_OFF);
- #endif
- dm9k_WriteReg(DM9K_REG_RCR, DM9K_RCR_SET);
- SendPackOk = 0;
- }
- void dm9k_phy_write(uint8_t phy_reg, uint16_t writedata)
- {
-
- dm9k_WriteReg(DM9K_REG_EPAR, phy_reg | DM9K_PHY);
-
- dm9k_WriteReg(DM9K_REG_EPDRH, (writedata >> 8) & 0xff);
- dm9k_WriteReg(DM9K_REG_EPDRL, writedata & 0xff);
- dm9k_WriteReg(DM9K_REG_EPCR, 0x0a);
- while (dm9k_ReadReg(DM9K_REG_EPCR) & 0x01)
- ;
- dm9k_WriteReg(DM9K_REG_EPCR, 0x08);
- }
- uint16_t dm9k_phy_read(uint8_t phy_reg)
- {
- uint16_t temp;
-
- dm9k_WriteReg(DM9K_REG_EPAR, phy_reg | DM9K_PHY);
-
- dm9k_WriteReg(DM9K_REG_EPCR, 0x0C);
- while (dm9k_ReadReg(DM9K_REG_EPCR) & 0x01)
- ;
- dm9k_WriteReg(DM9K_REG_EPCR, 0x00);
- temp = (dm9k_ReadReg(DM9K_REG_EPDRH) << 8) | (dm9k_ReadReg(DM9K_REG_EPDRL));
- return temp;
- }
- uint8_t dm9k_linkstat(void)
- {
- uint8_t linkchanged = 0;
- linkchanged = (dm9k_ReadReg(DM9K_PHY_BMSR) >> 6) & 0x01;
- return linkchanged;
- }
- uint8_t DM9K_Get_SpeedAndDuplex(void)
- {
- uint8_t temp;
- uint8_t i = 0;
- while (!(dm9k_phy_read(DM9K_PHY_BMSR) & 0x0020))
- {
- ms_delay(100);
- i++;
- if (i > 100)
- return 0XFF;
- }
- temp = ((dm9k_ReadReg(DM9K_REG_NSR) >> 6) & 0x02);
- temp |= ((dm9k_ReadReg(DM9K_REG_NCR) >> 3) & 0x01);
- return temp;
- }
- void dm9k_initnic(void)
- {
-
- if (DM9KA_ID != dm9k_ReadID())
- return;
- dm9k_WriteReg(DM9K_REG_GPCR, 0x01);
- dm9k_WriteReg(DM9K_REG_GPR, 0x00);
- ms_delay(5);
- dm9k_WriteReg(DM9K_REG_NCR, DM9K_REG_RESET);
- dm9k_udelay(100);
- dm9k_WriteReg(DM9K_REG_NCR, DM9K_REG_RESET);
- dm9k_udelay(100);
-
- dm9k_WriteReg(DM9K_REG_NCR, 0x00);
- dm9k_WriteReg(DM9K_REG_NSR, 0x2c);
- dm9k_WriteReg(DM9K_REG_TCR, 0x00);
- dm9k_WriteReg(DM9K_REG_ISR, 0x3f);
-
- dm9k_WriteReg(DM9K_REG_IMR, 0x80);
- dm9k_WriteReg(DM9K_REG_TCR2, 0x80);
- dm9k_WriteReg(DM9K_REG_BPTR, 0x3F);
- dm9k_WriteReg(DM9K_REG_FCTR, 0x38);
- dm9k_WriteReg(DM9K_REG_RCR, DM9K_RCR_SET);
- dm9k_hash_table(dm9kdev.mac);
- dm9k_WriteReg(DM9K_REG_GPR, DM9K_PHY_OFF);
- dm9k_phy_write(DM9K_PHY_BMCR, 0x8000);
-
- dm9k_phy_write(DM9K_PHY_BMCR, 0x1000);
- dm9k_phy_write(DM9K_PHY_ANAR, 0x01E1);
- dm9k_WriteReg(DM9K_REG_GPR, DM9K_PHY_ON);
-
-
-
-
-
-
-
-
-
- dm9k_WriteReg(DM9K_REG_IMR, DM9K_IMR_SET);
- EXTI_InitTypeDef EXTI_InitStructure;
- NVIC_InitTypeDef NVIC_InitStructure;
- SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, GPIO_PinSource15);
-
- EXTI_InitStructure.EXTI_Line = EXTI_Line15;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
- EXTI_ClearITPendingBit(EXTI_Line15);
- NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 8;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
- SendPackOk = 0;
- }
- uint16_t dm9k_receive_packet(uint8_t *_uip_buf)
- {
- uint16_t ReceiveLength;
- uint16_t *ReceiveData;
- uint8_t rx_int_count = 0;
- uint8_t rx_checkbyte;
- uint16_t rx_status, rx_length;
- uint8_t jump_packet;
- uint16_t i;
- uint16_t calc_len;
- uint16_t calc_MRR;
- do
- {
- ReceiveLength = 0;
- ReceiveData = (uint16_t *)_uip_buf;
- jump_packet = 0;
- dm9k_ReadReg(DM9K_REG_MRCMDX);
-
- calc_MRR = (dm9k_ReadReg(DM9K_REG_MRRH) << 8) + dm9k_ReadReg(DM9K_REG_MRRL);
- rx_checkbyte = dm9k_ReadReg(DM9K_REG_MRCMDX);
- if (rx_checkbyte == DM9K_PKT_RDY)
- {
-
- NET_REG_ADDR = DM9K_REG_MRCMD;
- rx_status = NET_REG_DATA;
- rx_length = NET_REG_DATA;
-
- if (rx_length > Max_Ethernet_Lenth)
- jump_packet = 1;
- #ifdef Broadcast_Jump
-
- if (rx_status & 0x4000)
- {
- if (rx_length > Max_Broadcast_Lenth)
- jump_packet = 1;
- }
- #endif
-
-
- calc_MRR += (rx_length + 4);
- if (rx_length & 0x01)
- calc_MRR++;
- if (calc_MRR > 0x3fff)
- calc_MRR -= 0x3400;
- if (jump_packet == 0x01)
- {
-
- dm9k_WriteReg(DM9K_REG_MRRH, (calc_MRR >> 8) & 0xff);
- dm9k_WriteReg(DM9K_REG_MRRL, calc_MRR & 0xff);
- continue;
- }
-
- calc_len = (rx_length + 1) >> 1;
- for (i = 0; i < calc_len; i++)
- ReceiveData[i] = NET_REG_DATA;
-
- ReceiveLength = rx_length - 4;
- rx_int_count++;
- #ifdef FifoPointCheck
- if (calc_MRR != ((dm9k_ReadReg(DM9K_REG_MRRH) << 8) + dm9k_ReadReg(DM9K_REG_MRRL)))
- {
- #ifdef Point_Error_Reset
- dm9k_reset();
- return ReceiveLength;
- #endif
-
- dm9k_WriteReg(DM9K_REG_MRRH, (calc_MRR >> 8) & 0xff);
- dm9k_WriteReg(DM9K_REG_MRRL, calc_MRR & 0xff);
- }
- #endif
- return ReceiveLength;
- }
- else
- {
- if (rx_checkbyte == DM9K_PKT_NORDY)
- {
- dm9k_WriteReg(DM9K_REG_ISR, 0x3f);
- }
- else
- {
- dm9k_initnic();
- }
- return (0);
- }
- } while (rx_int_count < Max_Int_Count);
- return 0;
- }
- void dm9k_send_packet(uint8_t *p_char, uint16_t length)
- {
- uint16_t SendLength = length;
- uint16_t *SendData = (uint16_t *)p_char;
- uint16_t i;
- uint16_t calc_len;
- __IO uint16_t calc_MWR;
- #ifdef FifoPointCheck
-
-
- calc_MWR = (dm9k_ReadReg(DM9K_REG_MWRH) << 8) + dm9k_ReadReg(DM9K_REG_MWRL);
- calc_MWR += SendLength;
- if (SendLength & 0x01)
- calc_MWR++;
- if (calc_MWR > 0x0bff)
- calc_MWR -= 0x0c00;
- #endif
- dm9k_WriteReg(DM9K_REG_TXPLH, (SendLength >> 8) & 0xff);
- dm9k_WriteReg(DM9K_REG_TXPLL, SendLength & 0xff);
-
- NET_REG_ADDR = DM9K_REG_MWCMD;
- calc_len = (SendLength + 1) >> 1;
- for (i = 0; i < calc_len; i++)
- {
- NET_REG_DATA = SendData[i];
- }
- dm9k_WriteReg(DM9K_REG_TCR, DM9K_TCR_SET);
- #ifdef FifoPointCheck
- if (calc_MWR != ((dm9k_ReadReg(DM9K_REG_MWRH) << 8) + dm9k_ReadReg(DM9K_REG_MWRL)))
- {
- #ifdef Point_Error_Reset
-
- while (dm9k_ReadReg(DM9K_REG_TCR) & DM9K_TCR_SET)
- dm9k_udelay(5);
- dm9k_reset();
- return;
- #endif
-
- dm9k_WriteReg(DM9K_REG_MWRH, (calc_MWR >> 8) & 0xff);
- dm9k_WriteReg(DM9K_REG_MWRL, calc_MWR & 0xff);
- }
- #endif
- return;
- }
- void dm9k_init(void)
- {
- dm9k_fsmc();
- s_FSMC_Init_Ok = 1;
- dm9k_initnic();
- }
- void etherdev_send(uint8_t *p_char, uint16_t length)
- {
- dm9k_send_packet(p_char, length);
- }
- uint16_t etherdev_read(uint8_t *p_char)
- {
- return dm9k_receive_packet(p_char);
- }
- void etherdev_chkmedia(void)
- {
-
- while (!(dm9k_ReadReg(DM9K_REG_NSR) & DM9K_PHY))
- {
- dm9k_udelay(2000);
- }
- }
- uint32_t dm9k_ReadID(void)
- {
- uint8_t vid1, vid2, pid1, pid2;
- if (s_FSMC_Init_Ok == 0)
- {
- dm9k_fsmc();
- s_FSMC_Init_Ok = 1;
- }
- vid1 = dm9k_ReadReg(DM9K_REG_VID_L) & 0xFF;
- vid2 = dm9k_ReadReg(DM9K_REG_VID_H) & 0xFF;
- pid1 = dm9k_ReadReg(DM9K_REG_PID_L) & 0xFF;
- pid2 = dm9k_ReadReg(DM9K_REG_PID_H) & 0xFF;
- return (pid2 << 24) | (pid1 << 16) | (vid2 << 8) | vid1;
- }
- static void dm9k_fsmc(void)
- {
- FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
- FSMC_NORSRAMTimingInitTypeDef p;
-
-
-
- p.FSMC_AddressSetupTime = 3;
- p.FSMC_AddressHoldTime = 0;
- p.FSMC_DataSetupTime = 3;
- p.FSMC_BusTurnAroundDuration = 0;
- p.FSMC_CLKDivision = 0;
- p.FSMC_DataLatency = 0;
- p.FSMC_AccessMode = FSMC_AccessMode_A;
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
- FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
-
- FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
- }
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