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@@ -476,40 +476,40 @@ void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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- SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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#endif
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- /* Reset the RCC clock configuration to the default reset state ------------*/
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- /* Set HSION bit */
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- RCC->CR |= (uint32_t)0x00000001;
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+ /* Reset the RCC clock configuration to the default reset state ------------*/
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+ /* Set HSION bit */
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+ RCC->CR |= (uint32_t)0x00000001;
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- /* Reset CFGR register */
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- RCC->CFGR = 0x00000000;
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+ /* Reset CFGR register */
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+ RCC->CFGR = 0x00000000;
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- /* Reset HSEON, CSSON and PLLON bits */
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- RCC->CR &= (uint32_t)0xFEF6FFFF;
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+ /* Reset HSEON, CSSON and PLLON bits */
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+ RCC->CR &= (uint32_t)0xFEF6FFFF;
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- /* Reset PLLCFGR register */
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- RCC->PLLCFGR = 0x24003010;
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+ /* Reset PLLCFGR register */
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+ RCC->PLLCFGR = 0x24003010;
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- /* Reset HSEBYP bit */
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- RCC->CR &= (uint32_t)0xFFFBFFFF;
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+ /* Reset HSEBYP bit */
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+ RCC->CR &= (uint32_t)0xFFFBFFFF;
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- /* Disable all interrupts */
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- RCC->CIR = 0x00000000;
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+ /* Disable all interrupts */
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+ RCC->CIR = 0x00000000;
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#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
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- SystemInit_ExtMemCtl();
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+ SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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- /* Configure the System clock source, PLL Multiplier and Divider factors,
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- AHB/APBx prescalers and Flash settings ----------------------------------*/
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- SetSysClock();
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+ /* Configure the System clock source, PLL Multiplier and Divider factors,
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+ AHB/APBx prescalers and Flash settings ----------------------------------*/
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+ SetSysClock();
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- /* Configure the Vector Table location add offset address ------------------*/
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+ /* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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@@ -551,88 +551,88 @@ void SystemInit(void)
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*/
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void SystemCoreClockUpdate(void)
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{
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- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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#if defined(STM32F446xx)
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- uint32_t pllr = 2;
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+ uint32_t pllr = 2;
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#endif /* STM32F446xx */
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- /* Get SYSCLK source -------------------------------------------------------*/
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- tmp = RCC->CFGR & RCC_CFGR_SWS;
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-
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- switch (tmp)
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- {
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- case 0x00: /* HSI used as system clock source */
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- SystemCoreClock = HSI_VALUE;
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- break;
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- case 0x04: /* HSE used as system clock source */
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- SystemCoreClock = HSE_VALUE;
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- break;
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- case 0x08: /* PLL P used as system clock source */
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- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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- SYSCLK = PLL_VCO / PLL_P
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- */
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- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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+ /* Get SYSCLK source -------------------------------------------------------*/
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+ tmp = RCC->CFGR & RCC_CFGR_SWS;
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-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)
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- if (pllsource != 0)
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- {
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- /* HSE used as PLL clock source */
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- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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- }
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- else
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+ switch (tmp)
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{
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- /* HSI used as PLL clock source */
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- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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- }
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+ case 0x00: /* HSI used as system clock source */
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+ SystemCoreClock = HSI_VALUE;
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+ break;
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+ case 0x04: /* HSE used as system clock source */
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+ SystemCoreClock = HSE_VALUE;
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+ break;
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+ case 0x08: /* PLL P used as system clock source */
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+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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+ SYSCLK = PLL_VCO / PLL_P
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+ */
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+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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+
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+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)
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+ if (pllsource != 0)
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+ {
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+ /* HSE used as PLL clock source */
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+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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+ }
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+ else
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+ {
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+ /* HSI used as PLL clock source */
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+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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+ }
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#elif defined(STM32F411xE)
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#if defined(USE_HSE_BYPASS)
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- if (pllsource != 0)
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- {
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- /* HSE used as PLL clock source */
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- pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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- }
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+ if (pllsource != 0)
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+ {
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+ /* HSE used as PLL clock source */
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+ pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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+ }
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#else
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- if (pllsource == 0)
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- {
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- /* HSI used as PLL clock source */
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- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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- }
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+ if (pllsource == 0)
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+ {
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+ /* HSI used as PLL clock source */
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+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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+ }
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#endif /* USE_HSE_BYPASS */
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx */
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- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
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- SystemCoreClock = pllvco / pllp;
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- break;
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+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
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+ SystemCoreClock = pllvco / pllp;
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+ break;
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#if defined(STM32F446xx)
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- case 0x0C: /* PLL R used as system clock source */
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- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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- SYSCLK = PLL_VCO / PLL_R
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- */
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- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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- if (pllsource != 0)
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- {
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- /* HSE used as PLL clock source */
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- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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- }
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- else
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- {
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- /* HSI used as PLL clock source */
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- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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- }
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-
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- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28) + 1) * 2;
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- SystemCoreClock = pllvco / pllr;
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- break;
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+ case 0x0C: /* PLL R used as system clock source */
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+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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+ SYSCLK = PLL_VCO / PLL_R
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+ */
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+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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+ if (pllsource != 0)
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+ {
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+ /* HSE used as PLL clock source */
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+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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+ }
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+ else
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+ {
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+ /* HSI used as PLL clock source */
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+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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+ }
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+
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+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28) + 1) * 2;
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+ SystemCoreClock = pllvco / pllr;
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+ break;
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#endif /* STM32F446xx */
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- default:
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- SystemCoreClock = HSI_VALUE;
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- break;
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- }
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- /* Compute HCLK frequency --------------------------------------------------*/
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- /* Get HCLK prescaler */
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- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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- /* HCLK frequency */
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- SystemCoreClock >>= tmp;
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+ default:
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+ SystemCoreClock = HSI_VALUE;
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+ break;
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+ }
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+ /* Compute HCLK frequency --------------------------------------------------*/
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+ /* Get HCLK prescaler */
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+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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+ /* HCLK frequency */
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+ SystemCoreClock >>= tmp;
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}
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/**
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@@ -646,140 +646,183 @@ void SystemCoreClockUpdate(void)
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static void SetSysClock(void)
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{
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)
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- /******************************************************************************/
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- /* PLL (clocked by HSE) used as System clock source */
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- /******************************************************************************/
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- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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-
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- /* Enable HSE */
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- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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-
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- /* Wait till HSE is ready and if Time out is reached exit */
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- do
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- {
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- HSEStatus = RCC->CR & RCC_CR_HSERDY;
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- StartUpCounter++;
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- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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-
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- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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- {
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- HSEStatus = (uint32_t)0x01;
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- }
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- else
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- {
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- HSEStatus = (uint32_t)0x00;
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- }
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-
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- if (HSEStatus == (uint32_t)0x01)
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- {
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- /* Select regulator voltage output Scale 1 mode */
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- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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- PWR->CR |= PWR_CR_VOS;
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+ /******************************************************************************/
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+ /* PLL (clocked by HSE) used as System clock source */
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+ /******************************************************************************/
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+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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- /* HCLK = SYSCLK / 1*/
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- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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+ /* Enable HSE */
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+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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+
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+ /* Wait till HSE is ready and if Time out is reached exit */
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+ do
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+ {
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+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
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+ StartUpCounter++;
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+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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+
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+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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+ {
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+ HSEStatus = (uint32_t)0x01;
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+ }
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+ else
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+ {
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+ HSEStatus = (uint32_t)0x00;
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+ }
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+
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+ if (HSEStatus == (uint32_t)0x01)
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+ {
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+ /* Select regulator voltage output Scale 1 mode */
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+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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+ PWR->CR |= PWR_CR_VOS;
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+
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+ /* HCLK = SYSCLK / 1*/
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+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
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- /* PCLK2 = HCLK / 2*/
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- RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
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+ /* PCLK2 = HCLK / 2*/
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+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
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- /* PCLK1 = HCLK / 4*/
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- RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
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+ /* PCLK1 = HCLK / 4*/
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+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
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#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F446xx */
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#if defined(STM32F401xx)
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- /* PCLK2 = HCLK / 2*/
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- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
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+ /* PCLK2 = HCLK / 2*/
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+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
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- /* PCLK1 = HCLK / 4*/
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- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
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+ /* PCLK1 = HCLK / 4*/
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+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
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#endif /* STM32F401xx */
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#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx)
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- /* Configure the main PLL */
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- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
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- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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+ /* Configure the main PLL */
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+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
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+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F401xx */
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#if defined(STM32F446xx)
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- /* Configure the main PLL */
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- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
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- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
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+ /* Configure the main PLL */
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+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
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+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
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#endif /* STM32F446xx */
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- /* Enable the main PLL */
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- RCC->CR |= RCC_CR_PLLON;
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+ /* Enable the main PLL */
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+ RCC->CR |= RCC_CR_PLLON;
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- /* Wait till the main PLL is ready */
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- while ((RCC->CR & RCC_CR_PLLRDY) == 0)
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- {
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- }
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+ /* Wait till the main PLL is ready */
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+ while ((RCC->CR & RCC_CR_PLLRDY) == 0)
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+ {
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+ }
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#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
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- /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
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- PWR->CR |= PWR_CR_ODEN;
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- while ((PWR->CSR & PWR_CSR_ODRDY) == 0)
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- {
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- }
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- PWR->CR |= PWR_CR_ODSWEN;
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- while ((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
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- {
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- }
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- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
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|
+ /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
|
|
+ PWR->CR |= PWR_CR_ODEN;
|
|
|
+ while ((PWR->CSR & PWR_CSR_ODRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ PWR->CR |= PWR_CR_ODSWEN;
|
|
|
+ while ((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
|
|
|
#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx */
|
|
|
|
|
|
#if defined(STM32F40_41xxx)
|
|
|
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
|
|
|
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS;
|
|
|
#endif /* STM32F40_41xxx */
|
|
|
|
|
|
#if defined(STM32F401xx)
|
|
|
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS;
|
|
|
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS;
|
|
|
#endif /* STM32F401xx */
|
|
|
|
|
|
- /* Select the main PLL as system clock source */
|
|
|
- RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
|
|
|
- RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
+ /* Select the main PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
|
|
|
- /* Wait till the main PLL is used as system clock source */
|
|
|
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
|
|
|
- {
|
|
|
- };
|
|
|
- }
|
|
|
- else
|
|
|
- { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
- configuration. User can add here some code to deal with this error */
|
|
|
- }
|
|
|
+ /* Wait till the main PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
|
|
|
+ {
|
|
|
+ };
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
#elif defined(STM32F411xE)
|
|
|
#if defined(USE_HSE_BYPASS)
|
|
|
- /******************************************************************************/
|
|
|
- /* PLL (clocked by HSE) used as System clock source */
|
|
|
- /******************************************************************************/
|
|
|
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
-
|
|
|
- /* Enable HSE and HSE BYPASS */
|
|
|
- RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
|
|
|
-
|
|
|
- /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
- do
|
|
|
- {
|
|
|
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
- StartUpCounter++;
|
|
|
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
-
|
|
|
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
- {
|
|
|
- HSEStatus = (uint32_t)0x01;
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- HSEStatus = (uint32_t)0x00;
|
|
|
- }
|
|
|
-
|
|
|
- if (HSEStatus == (uint32_t)0x01)
|
|
|
- {
|
|
|
+ /******************************************************************************/
|
|
|
+ /* PLL (clocked by HSE) used as System clock source */
|
|
|
+ /******************************************************************************/
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* Enable HSE and HSE BYPASS */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+ /* Select regulator voltage output Scale 1 mode */
|
|
|
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
|
|
+ PWR->CR |= PWR_CR_VOS;
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK / 1*/
|
|
|
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK / 2*/
|
|
|
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK / 4*/
|
|
|
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
|
|
|
+
|
|
|
+ /* Configure the main PLL */
|
|
|
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
|
|
|
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
|
|
+
|
|
|
+ /* Enable the main PLL */
|
|
|
+ RCC->CR |= RCC_CR_PLLON;
|
|
|
+
|
|
|
+ /* Wait till the main PLL is ready */
|
|
|
+ while ((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS;
|
|
|
+
|
|
|
+ /* Select the main PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
+
|
|
|
+ /* Wait till the main PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
|
|
|
+ ;
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+#else /* HSI will be used as PLL clock source */
|
|
|
/* Select regulator voltage output Scale 1 mode */
|
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
|
|
PWR->CR |= PWR_CR_VOS;
|
|
|
@@ -794,8 +837,7 @@ static void SetSysClock(void)
|
|
|
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
|
|
|
|
|
|
/* Configure the main PLL */
|
|
|
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
|
|
|
- (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
|
|
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) | (PLL_Q << 24);
|
|
|
|
|
|
/* Enable the main PLL */
|
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
@@ -814,51 +856,9 @@ static void SetSysClock(void)
|
|
|
|
|
|
/* Wait till the main PLL is used as system clock source */
|
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
|
|
|
- ;
|
|
|
+ ;
|
|
|
{
|
|
|
}
|
|
|
- }
|
|
|
- else
|
|
|
- { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
- configuration. User can add here some code to deal with this error */
|
|
|
- }
|
|
|
-#else /* HSI will be used as PLL clock source */
|
|
|
- /* Select regulator voltage output Scale 1 mode */
|
|
|
- RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
|
|
- PWR->CR |= PWR_CR_VOS;
|
|
|
-
|
|
|
- /* HCLK = SYSCLK / 1*/
|
|
|
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
|
|
-
|
|
|
- /* PCLK2 = HCLK / 2*/
|
|
|
- RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
|
|
|
-
|
|
|
- /* PCLK1 = HCLK / 4*/
|
|
|
- RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
|
|
|
-
|
|
|
- /* Configure the main PLL */
|
|
|
- RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) | (PLL_Q << 24);
|
|
|
-
|
|
|
- /* Enable the main PLL */
|
|
|
- RCC->CR |= RCC_CR_PLLON;
|
|
|
-
|
|
|
- /* Wait till the main PLL is ready */
|
|
|
- while ((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
- {
|
|
|
- }
|
|
|
-
|
|
|
- /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
|
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS;
|
|
|
-
|
|
|
- /* Select the main PLL as system clock source */
|
|
|
- RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
|
|
|
- RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
-
|
|
|
- /* Wait till the main PLL is used as system clock source */
|
|
|
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
|
|
|
- ;
|
|
|
- {
|
|
|
- }
|
|
|
#endif /* USE_HSE_BYPASS */
|
|
|
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
|
|
|
}
|
|
|
@@ -880,148 +880,148 @@ static void SetSysClock(void)
|
|
|
*/
|
|
|
void SystemInit_ExtMemCtl(void)
|
|
|
{
|
|
|
- /*-- GPIOs Configuration -----------------------------------------------------*/
|
|
|
- /*
|
|
|
- +-------------------+--------------------+------------------+--------------+
|
|
|
- + SRAM pins assignment +
|
|
|
- +-------------------+--------------------+------------------+--------------+
|
|
|
- | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
|
|
|
- | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
|
|
|
- | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
|
|
|
- | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
|
|
|
- | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
|
|
|
- | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
|
|
|
- | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
|
|
|
- | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
|
|
|
- | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
|
|
|
- | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
|
|
|
- | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
|
|
|
- | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
|
|
|
- | | PE15 <-> FMC_D12 |
|
|
|
- +------------------+------------------+
|
|
|
- */
|
|
|
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
|
|
- RCC->AHB1ENR |= 0x00000078;
|
|
|
-
|
|
|
- /* Connect PDx pins to FMC Alternate function */
|
|
|
- GPIOD->AFR[0] = 0x00cc00cc;
|
|
|
- GPIOD->AFR[1] = 0xcccccccc;
|
|
|
- /* Configure PDx pins in Alternate function mode */
|
|
|
- GPIOD->MODER = 0xaaaa0a0a;
|
|
|
- /* Configure PDx pins speed to 100 MHz */
|
|
|
- GPIOD->OSPEEDR = 0xffff0f0f;
|
|
|
- /* Configure PDx pins Output type to push-pull */
|
|
|
- GPIOD->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PDx pins */
|
|
|
- GPIOD->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PEx pins to FMC Alternate function */
|
|
|
- GPIOE->AFR[0] = 0xcccccccc;
|
|
|
- GPIOE->AFR[1] = 0xcccccccc;
|
|
|
- /* Configure PEx pins in Alternate function mode */
|
|
|
- GPIOE->MODER = 0xaaaaaaaa;
|
|
|
- /* Configure PEx pins speed to 100 MHz */
|
|
|
- GPIOE->OSPEEDR = 0xffffffff;
|
|
|
- /* Configure PEx pins Output type to push-pull */
|
|
|
- GPIOE->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PEx pins */
|
|
|
- GPIOE->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PFx pins to FMC Alternate function */
|
|
|
- GPIOF->AFR[0] = 0x00cccccc;
|
|
|
- GPIOF->AFR[1] = 0xcccc0000;
|
|
|
- /* Configure PFx pins in Alternate function mode */
|
|
|
- GPIOF->MODER = 0xaa000aaa;
|
|
|
- /* Configure PFx pins speed to 100 MHz */
|
|
|
- GPIOF->OSPEEDR = 0xff000fff;
|
|
|
- /* Configure PFx pins Output type to push-pull */
|
|
|
- GPIOF->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PFx pins */
|
|
|
- GPIOF->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PGx pins to FMC Alternate function */
|
|
|
- GPIOG->AFR[0] = 0x00cccccc;
|
|
|
- GPIOG->AFR[1] = 0x000000c0;
|
|
|
- /* Configure PGx pins in Alternate function mode */
|
|
|
- GPIOG->MODER = 0x00080aaa;
|
|
|
- /* Configure PGx pins speed to 100 MHz */
|
|
|
- GPIOG->OSPEEDR = 0x000c0fff;
|
|
|
- /* Configure PGx pins Output type to push-pull */
|
|
|
- GPIOG->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PGx pins */
|
|
|
- GPIOG->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /*-- FMC Configuration ------------------------------------------------------*/
|
|
|
- /* Enable the FMC/FSMC interface clock */
|
|
|
- RCC->AHB3ENR |= 0x00000001;
|
|
|
+ /*-- GPIOs Configuration -----------------------------------------------------*/
|
|
|
+ /*
|
|
|
+ +-------------------+--------------------+------------------+--------------+
|
|
|
+ + SRAM pins assignment +
|
|
|
+ +-------------------+--------------------+------------------+--------------+
|
|
|
+ | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
|
|
|
+ | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
|
|
|
+ | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
|
|
|
+ | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
|
|
|
+ | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
|
|
|
+ | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
|
|
|
+ | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
|
|
|
+ | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
|
|
|
+ | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
|
|
|
+ | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
|
|
|
+ | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
|
|
|
+ | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
|
|
|
+ | | PE15 <-> FMC_D12 |
|
|
|
+ +------------------+------------------+
|
|
|
+ */
|
|
|
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
|
|
+ RCC->AHB1ENR |= 0x00000078;
|
|
|
+
|
|
|
+ /* Connect PDx pins to FMC Alternate function */
|
|
|
+ GPIOD->AFR[0] = 0x00cc00cc;
|
|
|
+ GPIOD->AFR[1] = 0xcccccccc;
|
|
|
+ /* Configure PDx pins in Alternate function mode */
|
|
|
+ GPIOD->MODER = 0xaaaa0a0a;
|
|
|
+ /* Configure PDx pins speed to 100 MHz */
|
|
|
+ GPIOD->OSPEEDR = 0xffff0f0f;
|
|
|
+ /* Configure PDx pins Output type to push-pull */
|
|
|
+ GPIOD->OTYPER = 0x00000000;
|
|
|
+ /* No pull-up, pull-down for PDx pins */
|
|
|
+ GPIOD->PUPDR = 0x00000000;
|
|
|
+
|
|
|
+ /* Connect PEx pins to FMC Alternate function */
|
|
|
+ GPIOE->AFR[0] = 0xcccccccc;
|
|
|
+ GPIOE->AFR[1] = 0xcccccccc;
|
|
|
+ /* Configure PEx pins in Alternate function mode */
|
|
|
+ GPIOE->MODER = 0xaaaaaaaa;
|
|
|
+ /* Configure PEx pins speed to 100 MHz */
|
|
|
+ GPIOE->OSPEEDR = 0xffffffff;
|
|
|
+ /* Configure PEx pins Output type to push-pull */
|
|
|
+ GPIOE->OTYPER = 0x00000000;
|
|
|
+ /* No pull-up, pull-down for PEx pins */
|
|
|
+ GPIOE->PUPDR = 0x00000000;
|
|
|
+
|
|
|
+ /* Connect PFx pins to FMC Alternate function */
|
|
|
+ GPIOF->AFR[0] = 0x00cccccc;
|
|
|
+ GPIOF->AFR[1] = 0xcccc0000;
|
|
|
+ /* Configure PFx pins in Alternate function mode */
|
|
|
+ GPIOF->MODER = 0xaa000aaa;
|
|
|
+ /* Configure PFx pins speed to 100 MHz */
|
|
|
+ GPIOF->OSPEEDR = 0xff000fff;
|
|
|
+ /* Configure PFx pins Output type to push-pull */
|
|
|
+ GPIOF->OTYPER = 0x00000000;
|
|
|
+ /* No pull-up, pull-down for PFx pins */
|
|
|
+ GPIOF->PUPDR = 0x00000000;
|
|
|
+
|
|
|
+ /* Connect PGx pins to FMC Alternate function */
|
|
|
+ GPIOG->AFR[0] = 0x00cccccc;
|
|
|
+ GPIOG->AFR[1] = 0x000000c0;
|
|
|
+ /* Configure PGx pins in Alternate function mode */
|
|
|
+ GPIOG->MODER = 0x00080aaa;
|
|
|
+ /* Configure PGx pins speed to 100 MHz */
|
|
|
+ GPIOG->OSPEEDR = 0x000c0fff;
|
|
|
+ /* Configure PGx pins Output type to push-pull */
|
|
|
+ GPIOG->OTYPER = 0x00000000;
|
|
|
+ /* No pull-up, pull-down for PGx pins */
|
|
|
+ GPIOG->PUPDR = 0x00000000;
|
|
|
+
|
|
|
+ /*-- FMC Configuration ------------------------------------------------------*/
|
|
|
+ /* Enable the FMC/FSMC interface clock */
|
|
|
+ RCC->AHB3ENR |= 0x00000001;
|
|
|
|
|
|
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
|
|
|
- /* Configure and enable Bank1_SRAM2 */
|
|
|
- FMC_Bank1->BTCR[2] = 0x00001011;
|
|
|
- FMC_Bank1->BTCR[3] = 0x00000201;
|
|
|
- FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
|
|
+ /* Configure and enable Bank1_SRAM2 */
|
|
|
+ FMC_Bank1->BTCR[2] = 0x00001011;
|
|
|
+ FMC_Bank1->BTCR[3] = 0x00000201;
|
|
|
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
|
|
#endif /* STM32F427_437xx || STM32F429_439xx */
|
|
|
|
|
|
#if defined(STM32F40_41xxx)
|
|
|
- /* Configure and enable Bank1_SRAM2 */
|
|
|
- FSMC_Bank1->BTCR[2] = 0x00001011;
|
|
|
- FSMC_Bank1->BTCR[3] = 0x00000201;
|
|
|
- FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
|
|
+ /* Configure and enable Bank1_SRAM2 */
|
|
|
+ FSMC_Bank1->BTCR[2] = 0x00001011;
|
|
|
+ FSMC_Bank1->BTCR[3] = 0x00000201;
|
|
|
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
|
|
#endif /* STM32F40_41xxx */
|
|
|
|
|
|
- /*
|
|
|
- Bank1_SRAM2 is configured as follow:
|
|
|
- In case of FSMC configuration
|
|
|
- NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
|
|
|
- NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
|
|
|
- NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
|
|
|
- NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
|
|
|
- NORSRAMTimingStructure.FSMC_CLKDivision = 0;
|
|
|
- NORSRAMTimingStructure.FSMC_DataLatency = 0;
|
|
|
- NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
|
|
|
-
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
-
|
|
|
- In case of FMC configuration
|
|
|
- NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
|
|
|
- NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
|
|
|
- NORSRAMTimingStructure.FMC_DataSetupTime = 2;
|
|
|
- NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
|
|
|
- NORSRAMTimingStructure.FMC_CLKDivision = 0;
|
|
|
- NORSRAMTimingStructure.FMC_DataLatency = 0;
|
|
|
- NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
|
|
|
-
|
|
|
- FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
|
|
|
- FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
|
|
|
- FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
|
|
|
- FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
|
|
|
- FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
|
|
|
- FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
- FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
- */
|
|
|
+ /*
|
|
|
+ Bank1_SRAM2 is configured as follow:
|
|
|
+ In case of FSMC configuration
|
|
|
+ NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
|
|
|
+ NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
|
|
|
+ NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
|
|
|
+ NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
|
|
|
+ NORSRAMTimingStructure.FSMC_CLKDivision = 0;
|
|
|
+ NORSRAMTimingStructure.FSMC_DataLatency = 0;
|
|
|
+ NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
|
|
|
+
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
+
|
|
|
+ In case of FMC configuration
|
|
|
+ NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
|
|
|
+ NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
|
|
|
+ NORSRAMTimingStructure.FMC_DataSetupTime = 2;
|
|
|
+ NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
|
|
|
+ NORSRAMTimingStructure.FMC_CLKDivision = 0;
|
|
|
+ NORSRAMTimingStructure.FMC_DataLatency = 0;
|
|
|
+ NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
|
|
|
+
|
|
|
+ FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
+ FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
+ */
|
|
|
}
|
|
|
#endif /* DATA_IN_ExtSRAM */
|
|
|
|
|
|
@@ -1036,173 +1036,173 @@ void SystemInit_ExtMemCtl(void)
|
|
|
*/
|
|
|
void SystemInit_ExtMemCtl(void)
|
|
|
{
|
|
|
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
|
|
|
- register uint32_t index;
|
|
|
-
|
|
|
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
|
|
|
- clock */
|
|
|
- RCC->AHB1ENR |= 0x000001FC;
|
|
|
-
|
|
|
- /* Connect PCx pins to FMC Alternate function */
|
|
|
- GPIOC->AFR[0] = 0x0000000c;
|
|
|
- GPIOC->AFR[1] = 0x00007700;
|
|
|
- /* Configure PCx pins in Alternate function mode */
|
|
|
- GPIOC->MODER = 0x00a00002;
|
|
|
- /* Configure PCx pins speed to 50 MHz */
|
|
|
- GPIOC->OSPEEDR = 0x00a00002;
|
|
|
- /* Configure PCx pins Output type to push-pull */
|
|
|
- GPIOC->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PCx pins */
|
|
|
- GPIOC->PUPDR = 0x00500000;
|
|
|
-
|
|
|
- /* Connect PDx pins to FMC Alternate function */
|
|
|
- GPIOD->AFR[0] = 0x000000CC;
|
|
|
- GPIOD->AFR[1] = 0xCC000CCC;
|
|
|
- /* Configure PDx pins in Alternate function mode */
|
|
|
- GPIOD->MODER = 0xA02A000A;
|
|
|
- /* Configure PDx pins speed to 50 MHz */
|
|
|
- GPIOD->OSPEEDR = 0xA02A000A;
|
|
|
- /* Configure PDx pins Output type to push-pull */
|
|
|
- GPIOD->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PDx pins */
|
|
|
- GPIOD->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PEx pins to FMC Alternate function */
|
|
|
- GPIOE->AFR[0] = 0xC00000CC;
|
|
|
- GPIOE->AFR[1] = 0xCCCCCCCC;
|
|
|
- /* Configure PEx pins in Alternate function mode */
|
|
|
- GPIOE->MODER = 0xAAAA800A;
|
|
|
- /* Configure PEx pins speed to 50 MHz */
|
|
|
- GPIOE->OSPEEDR = 0xAAAA800A;
|
|
|
- /* Configure PEx pins Output type to push-pull */
|
|
|
- GPIOE->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PEx pins */
|
|
|
- GPIOE->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PFx pins to FMC Alternate function */
|
|
|
- GPIOF->AFR[0] = 0xcccccccc;
|
|
|
- GPIOF->AFR[1] = 0xcccccccc;
|
|
|
- /* Configure PFx pins in Alternate function mode */
|
|
|
- GPIOF->MODER = 0xAA800AAA;
|
|
|
- /* Configure PFx pins speed to 50 MHz */
|
|
|
- GPIOF->OSPEEDR = 0xAA800AAA;
|
|
|
- /* Configure PFx pins Output type to push-pull */
|
|
|
- GPIOF->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PFx pins */
|
|
|
- GPIOF->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PGx pins to FMC Alternate function */
|
|
|
- GPIOG->AFR[0] = 0xcccccccc;
|
|
|
- GPIOG->AFR[1] = 0xcccccccc;
|
|
|
- /* Configure PGx pins in Alternate function mode */
|
|
|
- GPIOG->MODER = 0xaaaaaaaa;
|
|
|
- /* Configure PGx pins speed to 50 MHz */
|
|
|
- GPIOG->OSPEEDR = 0xaaaaaaaa;
|
|
|
- /* Configure PGx pins Output type to push-pull */
|
|
|
- GPIOG->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PGx pins */
|
|
|
- GPIOG->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PHx pins to FMC Alternate function */
|
|
|
- GPIOH->AFR[0] = 0x00C0CC00;
|
|
|
- GPIOH->AFR[1] = 0xCCCCCCCC;
|
|
|
- /* Configure PHx pins in Alternate function mode */
|
|
|
- GPIOH->MODER = 0xAAAA08A0;
|
|
|
- /* Configure PHx pins speed to 50 MHz */
|
|
|
- GPIOH->OSPEEDR = 0xAAAA08A0;
|
|
|
- /* Configure PHx pins Output type to push-pull */
|
|
|
- GPIOH->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PHx pins */
|
|
|
- GPIOH->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /* Connect PIx pins to FMC Alternate function */
|
|
|
- GPIOI->AFR[0] = 0xCCCCCCCC;
|
|
|
- GPIOI->AFR[1] = 0x00000CC0;
|
|
|
- /* Configure PIx pins in Alternate function mode */
|
|
|
- GPIOI->MODER = 0x0028AAAA;
|
|
|
- /* Configure PIx pins speed to 50 MHz */
|
|
|
- GPIOI->OSPEEDR = 0x0028AAAA;
|
|
|
- /* Configure PIx pins Output type to push-pull */
|
|
|
- GPIOI->OTYPER = 0x00000000;
|
|
|
- /* No pull-up, pull-down for PIx pins */
|
|
|
- GPIOI->PUPDR = 0x00000000;
|
|
|
-
|
|
|
- /*-- FMC Configuration ------------------------------------------------------*/
|
|
|
- /* Enable the FMC interface clock */
|
|
|
- RCC->AHB3ENR |= 0x00000001;
|
|
|
-
|
|
|
- /* Configure and enable SDRAM bank1 */
|
|
|
- FMC_Bank5_6->SDCR[0] = 0x000039D0;
|
|
|
- FMC_Bank5_6->SDTR[0] = 0x01115351;
|
|
|
-
|
|
|
- /* SDRAM initialization sequence */
|
|
|
- /* Clock enable command */
|
|
|
- FMC_Bank5_6->SDCMR = 0x00000011;
|
|
|
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
|
- while ((tmpreg != 0) & (timeout-- > 0))
|
|
|
- {
|
|
|
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
|
- }
|
|
|
-
|
|
|
- /* Delay */
|
|
|
- for (index = 0; index < 1000; index++)
|
|
|
- ;
|
|
|
-
|
|
|
- /* PALL command */
|
|
|
- FMC_Bank5_6->SDCMR = 0x00000012;
|
|
|
- timeout = 0xFFFF;
|
|
|
- while ((tmpreg != 0) & (timeout-- > 0))
|
|
|
- {
|
|
|
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
|
- }
|
|
|
-
|
|
|
- /* Auto refresh command */
|
|
|
- FMC_Bank5_6->SDCMR = 0x00000073;
|
|
|
- timeout = 0xFFFF;
|
|
|
- while ((tmpreg != 0) & (timeout-- > 0))
|
|
|
- {
|
|
|
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
|
- }
|
|
|
-
|
|
|
- /* MRD register program */
|
|
|
- FMC_Bank5_6->SDCMR = 0x00046014;
|
|
|
- timeout = 0xFFFF;
|
|
|
- while ((tmpreg != 0) & (timeout-- > 0))
|
|
|
- {
|
|
|
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
|
- }
|
|
|
-
|
|
|
- /* Set refresh count */
|
|
|
- tmpreg = FMC_Bank5_6->SDRTR;
|
|
|
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1));
|
|
|
-
|
|
|
- /* Disable write protection */
|
|
|
- tmpreg = FMC_Bank5_6->SDCR[0];
|
|
|
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
|
|
-
|
|
|
- /*
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- Bank1_SDRAM is configured as follow:
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-
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- FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
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- FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
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- FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
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- FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
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- FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
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- FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
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- FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
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-
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- FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
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- FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
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- FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
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- FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
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- FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
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- FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
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- FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
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- FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
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- FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
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- FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
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- FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
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- */
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+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
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+ register uint32_t index;
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+
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+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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+ clock */
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+ RCC->AHB1ENR |= 0x000001FC;
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+
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+ /* Connect PCx pins to FMC Alternate function */
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+ GPIOC->AFR[0] = 0x0000000c;
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+ GPIOC->AFR[1] = 0x00007700;
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+ /* Configure PCx pins in Alternate function mode */
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+ GPIOC->MODER = 0x00a00002;
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+ /* Configure PCx pins speed to 50 MHz */
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+ GPIOC->OSPEEDR = 0x00a00002;
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+ /* Configure PCx pins Output type to push-pull */
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+ GPIOC->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PCx pins */
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+ GPIOC->PUPDR = 0x00500000;
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+
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+ /* Connect PDx pins to FMC Alternate function */
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+ GPIOD->AFR[0] = 0x000000CC;
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+ GPIOD->AFR[1] = 0xCC000CCC;
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+ /* Configure PDx pins in Alternate function mode */
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+ GPIOD->MODER = 0xA02A000A;
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+ /* Configure PDx pins speed to 50 MHz */
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+ GPIOD->OSPEEDR = 0xA02A000A;
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+ /* Configure PDx pins Output type to push-pull */
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+ GPIOD->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PDx pins */
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+ GPIOD->PUPDR = 0x00000000;
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+
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+ /* Connect PEx pins to FMC Alternate function */
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+ GPIOE->AFR[0] = 0xC00000CC;
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+ GPIOE->AFR[1] = 0xCCCCCCCC;
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+ /* Configure PEx pins in Alternate function mode */
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+ GPIOE->MODER = 0xAAAA800A;
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+ /* Configure PEx pins speed to 50 MHz */
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+ GPIOE->OSPEEDR = 0xAAAA800A;
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+ /* Configure PEx pins Output type to push-pull */
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+ GPIOE->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PEx pins */
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+ GPIOE->PUPDR = 0x00000000;
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+
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+ /* Connect PFx pins to FMC Alternate function */
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+ GPIOF->AFR[0] = 0xcccccccc;
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+ GPIOF->AFR[1] = 0xcccccccc;
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+ /* Configure PFx pins in Alternate function mode */
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+ GPIOF->MODER = 0xAA800AAA;
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+ /* Configure PFx pins speed to 50 MHz */
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+ GPIOF->OSPEEDR = 0xAA800AAA;
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+ /* Configure PFx pins Output type to push-pull */
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+ GPIOF->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PFx pins */
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+ GPIOF->PUPDR = 0x00000000;
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+
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+ /* Connect PGx pins to FMC Alternate function */
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+ GPIOG->AFR[0] = 0xcccccccc;
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+ GPIOG->AFR[1] = 0xcccccccc;
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+ /* Configure PGx pins in Alternate function mode */
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+ GPIOG->MODER = 0xaaaaaaaa;
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+ /* Configure PGx pins speed to 50 MHz */
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+ GPIOG->OSPEEDR = 0xaaaaaaaa;
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+ /* Configure PGx pins Output type to push-pull */
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+ GPIOG->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PGx pins */
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+ GPIOG->PUPDR = 0x00000000;
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+
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+ /* Connect PHx pins to FMC Alternate function */
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+ GPIOH->AFR[0] = 0x00C0CC00;
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+ GPIOH->AFR[1] = 0xCCCCCCCC;
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+ /* Configure PHx pins in Alternate function mode */
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+ GPIOH->MODER = 0xAAAA08A0;
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+ /* Configure PHx pins speed to 50 MHz */
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+ GPIOH->OSPEEDR = 0xAAAA08A0;
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+ /* Configure PHx pins Output type to push-pull */
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+ GPIOH->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PHx pins */
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+ GPIOH->PUPDR = 0x00000000;
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+
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+ /* Connect PIx pins to FMC Alternate function */
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+ GPIOI->AFR[0] = 0xCCCCCCCC;
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+ GPIOI->AFR[1] = 0x00000CC0;
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+ /* Configure PIx pins in Alternate function mode */
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+ GPIOI->MODER = 0x0028AAAA;
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+ /* Configure PIx pins speed to 50 MHz */
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+ GPIOI->OSPEEDR = 0x0028AAAA;
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+ /* Configure PIx pins Output type to push-pull */
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+ GPIOI->OTYPER = 0x00000000;
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+ /* No pull-up, pull-down for PIx pins */
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+ GPIOI->PUPDR = 0x00000000;
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+
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+ /*-- FMC Configuration ------------------------------------------------------*/
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+ /* Enable the FMC interface clock */
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+ RCC->AHB3ENR |= 0x00000001;
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+
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+ /* Configure and enable SDRAM bank1 */
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+ FMC_Bank5_6->SDCR[0] = 0x000039D0;
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+ FMC_Bank5_6->SDTR[0] = 0x01115351;
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+
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+ /* SDRAM initialization sequence */
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+ /* Clock enable command */
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+ FMC_Bank5_6->SDCMR = 0x00000011;
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+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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+ while ((tmpreg != 0) & (timeout-- > 0))
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+ {
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+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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+ }
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+
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+ /* Delay */
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+ for (index = 0; index < 1000; index++)
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+ ;
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+
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+ /* PALL command */
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+ FMC_Bank5_6->SDCMR = 0x00000012;
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+ timeout = 0xFFFF;
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+ while ((tmpreg != 0) & (timeout-- > 0))
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+ {
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+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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+ }
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+
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+ /* Auto refresh command */
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+ FMC_Bank5_6->SDCMR = 0x00000073;
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+ timeout = 0xFFFF;
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+ while ((tmpreg != 0) & (timeout-- > 0))
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+ {
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+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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+ }
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+
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+ /* MRD register program */
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+ FMC_Bank5_6->SDCMR = 0x00046014;
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+ timeout = 0xFFFF;
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+ while ((tmpreg != 0) & (timeout-- > 0))
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+ {
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+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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+ }
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+
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+ /* Set refresh count */
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+ tmpreg = FMC_Bank5_6->SDRTR;
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+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1));
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+
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+ /* Disable write protection */
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+ tmpreg = FMC_Bank5_6->SDCR[0];
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+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
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+
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+ /*
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+ Bank1_SDRAM is configured as follow:
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+
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+ FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
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+ FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
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+ FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
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+ FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
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+ FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
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+ FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
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+ FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
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+
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+ FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
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+ FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
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+ FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
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+ FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
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+ FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
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+ FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
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+ FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
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+ FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
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+ FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
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+ FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
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+ FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
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+ */
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}
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#endif /* DATA_IN_ExtSDRAM */
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