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<div id="projectname">CMSIS-CORE
 <span id="projectnumber">Version 4.00</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<div class="title">Overview </div> </div>
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<div class="textblock"><p>CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
<ul>
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
</ul>
<hr/>
<p>This chapter provides details about the CMSIS-CORE and contains the following sections:</p>
<ul>
<li><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
<li><a class="el" href="_templates_pg.html">Template Files</a> describes the files of the CMSIS-CORE in detail and explains how to adapt template files provided by ARM to silicon vendor devices.</li>
<li><a class="el" href="_c_o_r_e__m_i_s_r_a__exceptions_pg.html">MISRA-C:2004 Compliance Exceptions</a> describes the violations to the MISRA standard.</li>
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
</ul>
<hr/>
<h2>CMSIS-CORE in ARM::CMSIS Pack</h2>
<p>Files relevant to CMSIS-CORE are present in the following <b>ARM::CMSIS</b> directories: </p>
<table class="doxtable">
<tr>
<th>File/Folder </th><th>Content </th></tr>
<tr>
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
<tr>
<td><b>CMSIS\Include</b> </td><td>CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
<tr>
<td><b>Device</b> </td><td><a class="el" href="_using__a_r_m_pg.html">ARM reference implementations</a> of Cortex-M devices </td></tr>
<tr>
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="_templates_pg.html">Template Files</a> for extension by silicon vendors </td></tr>
</table>
<hr/>
<h1><a class="anchor" id="ref_man_sec"></a>
Cortex-M Reference Manuals</h1>
<p>The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.</p>
<ul>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a></li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a></li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a></li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a></li>
</ul>
<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000001">Todo:</a></b></dt><dd><ul>
<li><a href="" target="_blank"><b>Link to Cortex-M7 Devices Generic User Guide</b></a></li>
</ul>
</dd></dl>
<hr/>
<h1><a class="anchor" id="tested_tools_sec"></a>
Tested and Verified Toolchains</h1>
<p>The CMSIS-CORE <a class="el" href="_templates_pg.html">Template Files</a> supplied by ARM have been tested and verified with the following toolchains:</p>
<ul>
<li>ARM: MDK-ARM Version 5.12</li>
<li>GNU: GNU Tools ARM Embedded 4.8 2014.q3</li>
<li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
</ul>
<hr/>
<h2><a class="anchor" id="core_revisionHistory"></a>Revision History of CMSIS-CORE</h2>
<table class="cmtable" summary="Core Exception Name">
<tr>
<th>Version </th><th>Description </th></tr>
<tr>
<td>V4.00 </td><td>Added: Cortex-M7 support.<br/>
Added: intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> <br/>
</td></tr>
<tr>
<td>V3.40 </td><td>Corrected: C++ include guard settings.<br/>
</td></tr>
<tr>
<td>V3.30 </td><td>Added: COSMIC tool chain support.<br/>
Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.<br/>
Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.<br/>
Corrected: GCC/CLang warnings.<br/>
</td></tr>
<tr>
<td>V3.20 </td><td>Added: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic.<br/>
Added: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4.<br/>
Corrected: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a>.<br/>
Corrected: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler.<br/>
Corrected: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.<br/>
</td></tr>
<tr>
<td>V3.01 </td><td>Added support for Cortex-M0+ processor. <br/>
</td></tr>
<tr>
<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br/>
Added function <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>.<br/>
Added <a class="el" href="_reg_map_pg.html">Register Mapping</a> for TPIU, DWT. <br/>
Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br/>
Corrected <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br/>
Corrected the functions <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br/>
Documentation restructured. </td></tr>
<tr>
<td>V2.10 </td><td>Updated documentation.<br/>
Updated CMSIS core include files.<br/>
Changed CMSIS/Device folder structure.<br/>
Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br/>
Reworked CMSIS DSP library examples. </td></tr>
<tr>
<td>V2.00 </td><td>Added support for Cortex-M4 processor. </td></tr>
<tr>
<td>V1.30 </td><td>Reworked Startup Concept.<br/>
Added additional Debug Functionality.<br/>
Changed folder structure.<br/>
Added doxygen comments.<br/>
Added definitions for bit. </td></tr>
<tr>
<td>V1.01 </td><td>Added support for Cortex-M0 processor. </td></tr>
<tr>
<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> </td></tr>
<tr>
<td>V1.00 </td><td>Initial Release for Cortex-M3 processor. </td></tr>
</table>
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