mpu_armv8.h 11 KB

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  1. /******************************************************************************
  2. * @file mpu_armv8.h
  3. * @brief CMSIS MPU API for Armv8-M MPU
  4. * @version V5.0.4
  5. * @date 10. January 2018
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. #if defined ( __ICCARM__ )
  25. #pragma system_include /* treat file as system include file for MISRA check */
  26. #elif defined (__clang__)
  27. #pragma clang system_header /* treat file as system include file */
  28. #endif
  29. #ifndef ARM_MPU_ARMV8_H
  30. #define ARM_MPU_ARMV8_H
  31. /** \brief Attribute for device memory (outer only) */
  32. #define ARM_MPU_ATTR_DEVICE ( 0U )
  33. /** \brief Attribute for non-cacheable, normal memory */
  34. #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
  35. /** \brief Attribute for normal memory (outer and inner)
  36. * \param NT Non-Transient: Set to 1 for non-transient data.
  37. * \param WB Write-Back: Set to 1 to use write-back update policy.
  38. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
  39. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
  40. */
  41. #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
  42. (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
  43. /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
  44. #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
  45. /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
  46. #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
  47. /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
  48. #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
  49. /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
  50. #define ARM_MPU_ATTR_DEVICE_GRE (3U)
  51. /** \brief Memory Attribute
  52. * \param O Outer memory attributes
  53. * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
  54. */
  55. #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
  56. /** \brief Normal memory non-shareable */
  57. #define ARM_MPU_SH_NON (0U)
  58. /** \brief Normal memory outer shareable */
  59. #define ARM_MPU_SH_OUTER (2U)
  60. /** \brief Normal memory inner shareable */
  61. #define ARM_MPU_SH_INNER (3U)
  62. /** \brief Memory access permissions
  63. * \param RO Read-Only: Set to 1 for read-only memory.
  64. * \param NP Non-Privileged: Set to 1 for non-privileged memory.
  65. */
  66. #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
  67. /** \brief Region Base Address Register value
  68. * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
  69. * \param SH Defines the Shareability domain for this memory region.
  70. * \param RO Read-Only: Set to 1 for a read-only memory region.
  71. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
  72. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
  73. */
  74. #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
  75. ((BASE & MPU_RBAR_BASE_Msk) | \
  76. ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
  77. ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
  78. ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
  79. /** \brief Region Limit Address Register value
  80. * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
  81. * \param IDX The attribute index to be associated with this memory region.
  82. */
  83. #define ARM_MPU_RLAR(LIMIT, IDX) \
  84. ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
  85. ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
  86. (MPU_RLAR_EN_Msk))
  87. /**
  88. * Struct for a single MPU Region
  89. */
  90. typedef struct {
  91. uint32_t RBAR; /*!< Region Base Address Register value */
  92. uint32_t RLAR; /*!< Region Limit Address Register value */
  93. } ARM_MPU_Region_t;
  94. /** Enable the MPU.
  95. * \param MPU_Control Default access permissions for unconfigured regions.
  96. */
  97. __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
  98. {
  99. __DSB();
  100. __ISB();
  101. MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
  102. #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  103. SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
  104. #endif
  105. }
  106. /** Disable the MPU.
  107. */
  108. __STATIC_INLINE void ARM_MPU_Disable(void)
  109. {
  110. __DSB();
  111. __ISB();
  112. #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  113. SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
  114. #endif
  115. MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
  116. }
  117. #ifdef MPU_NS
  118. /** Enable the Non-secure MPU.
  119. * \param MPU_Control Default access permissions for unconfigured regions.
  120. */
  121. __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
  122. {
  123. __DSB();
  124. __ISB();
  125. MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
  126. #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  127. SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
  128. #endif
  129. }
  130. /** Disable the Non-secure MPU.
  131. */
  132. __STATIC_INLINE void ARM_MPU_Disable_NS(void)
  133. {
  134. __DSB();
  135. __ISB();
  136. #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  137. SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
  138. #endif
  139. MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
  140. }
  141. #endif
  142. /** Set the memory attribute encoding to the given MPU.
  143. * \param mpu Pointer to the MPU to be configured.
  144. * \param idx The attribute index to be set [0-7]
  145. * \param attr The attribute value to be set.
  146. */
  147. __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
  148. {
  149. const uint8_t reg = idx / 4U;
  150. const uint32_t pos = ((idx % 4U) * 8U);
  151. const uint32_t mask = 0xFFU << pos;
  152. if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
  153. return; // invalid index
  154. }
  155. mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
  156. }
  157. /** Set the memory attribute encoding.
  158. * \param idx The attribute index to be set [0-7]
  159. * \param attr The attribute value to be set.
  160. */
  161. __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
  162. {
  163. ARM_MPU_SetMemAttrEx(MPU, idx, attr);
  164. }
  165. #ifdef MPU_NS
  166. /** Set the memory attribute encoding to the Non-secure MPU.
  167. * \param idx The attribute index to be set [0-7]
  168. * \param attr The attribute value to be set.
  169. */
  170. __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
  171. {
  172. ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
  173. }
  174. #endif
  175. /** Clear and disable the given MPU region of the given MPU.
  176. * \param mpu Pointer to MPU to be used.
  177. * \param rnr Region number to be cleared.
  178. */
  179. __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
  180. {
  181. mpu->RNR = rnr;
  182. mpu->RLAR = 0U;
  183. }
  184. /** Clear and disable the given MPU region.
  185. * \param rnr Region number to be cleared.
  186. */
  187. __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
  188. {
  189. ARM_MPU_ClrRegionEx(MPU, rnr);
  190. }
  191. #ifdef MPU_NS
  192. /** Clear and disable the given Non-secure MPU region.
  193. * \param rnr Region number to be cleared.
  194. */
  195. __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
  196. {
  197. ARM_MPU_ClrRegionEx(MPU_NS, rnr);
  198. }
  199. #endif
  200. /** Configure the given MPU region of the given MPU.
  201. * \param mpu Pointer to MPU to be used.
  202. * \param rnr Region number to be configured.
  203. * \param rbar Value for RBAR register.
  204. * \param rlar Value for RLAR register.
  205. */
  206. __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
  207. {
  208. mpu->RNR = rnr;
  209. mpu->RBAR = rbar;
  210. mpu->RLAR = rlar;
  211. }
  212. /** Configure the given MPU region.
  213. * \param rnr Region number to be configured.
  214. * \param rbar Value for RBAR register.
  215. * \param rlar Value for RLAR register.
  216. */
  217. __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
  218. {
  219. ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
  220. }
  221. #ifdef MPU_NS
  222. /** Configure the given Non-secure MPU region.
  223. * \param rnr Region number to be configured.
  224. * \param rbar Value for RBAR register.
  225. * \param rlar Value for RLAR register.
  226. */
  227. __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
  228. {
  229. ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
  230. }
  231. #endif
  232. /** Memcopy with strictly ordered memory access, e.g. for register targets.
  233. * \param dst Destination data is copied to.
  234. * \param src Source data is copied from.
  235. * \param len Amount of data words to be copied.
  236. */
  237. __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
  238. {
  239. uint32_t i;
  240. for (i = 0U; i < len; ++i)
  241. {
  242. dst[i] = src[i];
  243. }
  244. }
  245. /** Load the given number of MPU regions from a table to the given MPU.
  246. * \param mpu Pointer to the MPU registers to be used.
  247. * \param rnr First region number to be configured.
  248. * \param table Pointer to the MPU configuration table.
  249. * \param cnt Amount of regions to be configured.
  250. */
  251. __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
  252. {
  253. const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  254. if (cnt == 1U) {
  255. mpu->RNR = rnr;
  256. orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
  257. } else {
  258. uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
  259. uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
  260. mpu->RNR = rnrBase;
  261. while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
  262. uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
  263. orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
  264. table += c;
  265. cnt -= c;
  266. rnrOffset = 0U;
  267. rnrBase += MPU_TYPE_RALIASES;
  268. mpu->RNR = rnrBase;
  269. }
  270. orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
  271. }
  272. }
  273. /** Load the given number of MPU regions from a table.
  274. * \param rnr First region number to be configured.
  275. * \param table Pointer to the MPU configuration table.
  276. * \param cnt Amount of regions to be configured.
  277. */
  278. __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
  279. {
  280. ARM_MPU_LoadEx(MPU, rnr, table, cnt);
  281. }
  282. #ifdef MPU_NS
  283. /** Load the given number of MPU regions from a table to the Non-secure MPU.
  284. * \param rnr First region number to be configured.
  285. * \param table Pointer to the MPU configuration table.
  286. * \param cnt Amount of regions to be configured.
  287. */
  288. __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
  289. {
  290. ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
  291. }
  292. #endif
  293. #endif