cmsis_iccarm.h 28 KB

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  1. /**************************************************************************//**
  2. * @file cmsis_iccarm.h
  3. * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
  4. * @version V5.0.7
  5. * @date 19. June 2018
  6. ******************************************************************************/
  7. //------------------------------------------------------------------------------
  8. //
  9. // Copyright (c) 2017-2018 IAR Systems
  10. //
  11. // Licensed under the Apache License, Version 2.0 (the "License")
  12. // you may not use this file except in compliance with the License.
  13. // You may obtain a copy of the License at
  14. // http://www.apache.org/licenses/LICENSE-2.0
  15. //
  16. // Unless required by applicable law or agreed to in writing, software
  17. // distributed under the License is distributed on an "AS IS" BASIS,
  18. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  19. // See the License for the specific language governing permissions and
  20. // limitations under the License.
  21. //
  22. //------------------------------------------------------------------------------
  23. #ifndef __CMSIS_ICCARM_H__
  24. #define __CMSIS_ICCARM_H__
  25. #ifndef __ICCARM__
  26. #error This file should only be compiled by ICCARM
  27. #endif
  28. #pragma system_include
  29. #define __IAR_FT _Pragma("inline=forced") __intrinsic
  30. #if (__VER__ >= 8000000)
  31. #define __ICCARM_V8 1
  32. #else
  33. #define __ICCARM_V8 0
  34. #endif
  35. #ifndef __ALIGNED
  36. #if __ICCARM_V8
  37. #define __ALIGNED(x) __attribute__((aligned(x)))
  38. #elif (__VER__ >= 7080000)
  39. /* Needs IAR language extensions */
  40. #define __ALIGNED(x) __attribute__((aligned(x)))
  41. #else
  42. #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
  43. #define __ALIGNED(x)
  44. #endif
  45. #endif
  46. /* Define compiler macros for CPU architecture, used in CMSIS 5.
  47. */
  48. #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
  49. /* Macros already defined */
  50. #else
  51. #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
  52. #define __ARM_ARCH_8M_MAIN__ 1
  53. #elif defined(__ARM8M_BASELINE__)
  54. #define __ARM_ARCH_8M_BASE__ 1
  55. #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
  56. #if __ARM_ARCH == 6
  57. #define __ARM_ARCH_6M__ 1
  58. #elif __ARM_ARCH == 7
  59. #if __ARM_FEATURE_DSP
  60. #define __ARM_ARCH_7EM__ 1
  61. #else
  62. #define __ARM_ARCH_7M__ 1
  63. #endif
  64. #endif /* __ARM_ARCH */
  65. #endif /* __ARM_ARCH_PROFILE == 'M' */
  66. #endif
  67. /* Alternativ core deduction for older ICCARM's */
  68. #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
  69. !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
  70. #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
  71. #define __ARM_ARCH_6M__ 1
  72. #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
  73. #define __ARM_ARCH_7M__ 1
  74. #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
  75. #define __ARM_ARCH_7EM__ 1
  76. #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
  77. #define __ARM_ARCH_8M_BASE__ 1
  78. #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
  79. #define __ARM_ARCH_8M_MAIN__ 1
  80. #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
  81. #define __ARM_ARCH_8M_MAIN__ 1
  82. #else
  83. #error "Unknown target."
  84. #endif
  85. #endif
  86. #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
  87. #define __IAR_M0_FAMILY 1
  88. #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
  89. #define __IAR_M0_FAMILY 1
  90. #else
  91. #define __IAR_M0_FAMILY 0
  92. #endif
  93. #ifndef __ASM
  94. #define __ASM __asm
  95. #endif
  96. #ifndef __INLINE
  97. #define __INLINE inline
  98. #endif
  99. #ifndef __NO_RETURN
  100. #if __ICCARM_V8
  101. #define __NO_RETURN __attribute__((__noreturn__))
  102. #else
  103. #define __NO_RETURN _Pragma("object_attribute=__noreturn")
  104. #endif
  105. #endif
  106. #ifndef __PACKED
  107. #if __ICCARM_V8
  108. #define __PACKED __attribute__((packed, aligned(1)))
  109. #else
  110. /* Needs IAR language extensions */
  111. #define __PACKED __packed
  112. #endif
  113. #endif
  114. #ifndef __PACKED_STRUCT
  115. #if __ICCARM_V8
  116. #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
  117. #else
  118. /* Needs IAR language extensions */
  119. #define __PACKED_STRUCT __packed struct
  120. #endif
  121. #endif
  122. #ifndef __PACKED_UNION
  123. #if __ICCARM_V8
  124. #define __PACKED_UNION union __attribute__((packed, aligned(1)))
  125. #else
  126. /* Needs IAR language extensions */
  127. #define __PACKED_UNION __packed union
  128. #endif
  129. #endif
  130. #ifndef __RESTRICT
  131. #define __RESTRICT __restrict
  132. #endif
  133. #ifndef __STATIC_INLINE
  134. #define __STATIC_INLINE static inline
  135. #endif
  136. #ifndef __FORCEINLINE
  137. #define __FORCEINLINE _Pragma("inline=forced")
  138. #endif
  139. #ifndef __STATIC_FORCEINLINE
  140. #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
  141. #endif
  142. #ifndef __UNALIGNED_UINT16_READ
  143. #pragma language=save
  144. #pragma language=extended
  145. __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
  146. {
  147. return *(__packed uint16_t*)(ptr);
  148. }
  149. #pragma language=restore
  150. #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
  151. #endif
  152. #ifndef __UNALIGNED_UINT16_WRITE
  153. #pragma language=save
  154. #pragma language=extended
  155. __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
  156. {
  157. *(__packed uint16_t*)(ptr) = val;;
  158. }
  159. #pragma language=restore
  160. #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
  161. #endif
  162. #ifndef __UNALIGNED_UINT32_READ
  163. #pragma language=save
  164. #pragma language=extended
  165. __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
  166. {
  167. return *(__packed uint32_t*)(ptr);
  168. }
  169. #pragma language=restore
  170. #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
  171. #endif
  172. #ifndef __UNALIGNED_UINT32_WRITE
  173. #pragma language=save
  174. #pragma language=extended
  175. __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
  176. {
  177. *(__packed uint32_t*)(ptr) = val;;
  178. }
  179. #pragma language=restore
  180. #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
  181. #endif
  182. #ifndef __UNALIGNED_UINT32 /* deprecated */
  183. #pragma language=save
  184. #pragma language=extended
  185. __packed struct __iar_u32 { uint32_t v; };
  186. #pragma language=restore
  187. #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
  188. #endif
  189. #ifndef __USED
  190. #if __ICCARM_V8
  191. #define __USED __attribute__((used))
  192. #else
  193. #define __USED _Pragma("__root")
  194. #endif
  195. #endif
  196. #ifndef __WEAK
  197. #if __ICCARM_V8
  198. #define __WEAK __attribute__((weak))
  199. #else
  200. #define __WEAK _Pragma("__weak")
  201. #endif
  202. #endif
  203. #ifndef __ICCARM_INTRINSICS_VERSION__
  204. #define __ICCARM_INTRINSICS_VERSION__ 0
  205. #endif
  206. #if __ICCARM_INTRINSICS_VERSION__ == 2
  207. #if defined(__CLZ)
  208. #undef __CLZ
  209. #endif
  210. #if defined(__REVSH)
  211. #undef __REVSH
  212. #endif
  213. #if defined(__RBIT)
  214. #undef __RBIT
  215. #endif
  216. #if defined(__SSAT)
  217. #undef __SSAT
  218. #endif
  219. #if defined(__USAT)
  220. #undef __USAT
  221. #endif
  222. #include "iccarm_builtin.h"
  223. #define __disable_fault_irq __iar_builtin_disable_fiq
  224. #define __disable_irq __iar_builtin_disable_interrupt
  225. #define __enable_fault_irq __iar_builtin_enable_fiq
  226. #define __enable_irq __iar_builtin_enable_interrupt
  227. #define __arm_rsr __iar_builtin_rsr
  228. #define __arm_wsr __iar_builtin_wsr
  229. #define __get_APSR() (__arm_rsr("APSR"))
  230. #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
  231. #define __get_CONTROL() (__arm_rsr("CONTROL"))
  232. #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
  233. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  234. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  235. #define __get_FPSCR() (__arm_rsr("FPSCR"))
  236. #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
  237. #else
  238. #define __get_FPSCR() ( 0 )
  239. #define __set_FPSCR(VALUE) ((void)VALUE)
  240. #endif
  241. #define __get_IPSR() (__arm_rsr("IPSR"))
  242. #define __get_MSP() (__arm_rsr("MSP"))
  243. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  244. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  245. // without main extensions, the non-secure MSPLIM is RAZ/WI
  246. #define __get_MSPLIM() (0U)
  247. #else
  248. #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
  249. #endif
  250. #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
  251. #define __get_PSP() (__arm_rsr("PSP"))
  252. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  253. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  254. // without main extensions, the non-secure PSPLIM is RAZ/WI
  255. #define __get_PSPLIM() (0U)
  256. #else
  257. #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
  258. #endif
  259. #define __get_xPSR() (__arm_rsr("xPSR"))
  260. #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
  261. #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
  262. #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
  263. #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
  264. #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
  265. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  266. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  267. // without main extensions, the non-secure MSPLIM is RAZ/WI
  268. #define __set_MSPLIM(VALUE) ((void)(VALUE))
  269. #else
  270. #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
  271. #endif
  272. #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
  273. #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
  274. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  275. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  276. // without main extensions, the non-secure PSPLIM is RAZ/WI
  277. #define __set_PSPLIM(VALUE) ((void)(VALUE))
  278. #else
  279. #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
  280. #endif
  281. #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
  282. #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
  283. #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
  284. #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
  285. #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
  286. #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
  287. #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
  288. #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
  289. #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
  290. #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
  291. #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
  292. #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
  293. #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
  294. #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
  295. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  296. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  297. // without main extensions, the non-secure PSPLIM is RAZ/WI
  298. #define __TZ_get_PSPLIM_NS() (0U)
  299. #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
  300. #else
  301. #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
  302. #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
  303. #endif
  304. #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
  305. #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
  306. #define __NOP __iar_builtin_no_operation
  307. #define __CLZ __iar_builtin_CLZ
  308. #define __CLREX __iar_builtin_CLREX
  309. #define __DMB __iar_builtin_DMB
  310. #define __DSB __iar_builtin_DSB
  311. #define __ISB __iar_builtin_ISB
  312. #define __LDREXB __iar_builtin_LDREXB
  313. #define __LDREXH __iar_builtin_LDREXH
  314. #define __LDREXW __iar_builtin_LDREX
  315. #define __RBIT __iar_builtin_RBIT
  316. #define __REV __iar_builtin_REV
  317. #define __REV16 __iar_builtin_REV16
  318. __IAR_FT int16_t __REVSH(int16_t val)
  319. {
  320. return (int16_t) __iar_builtin_REVSH(val);
  321. }
  322. #define __ROR __iar_builtin_ROR
  323. #define __RRX __iar_builtin_RRX
  324. #define __SEV __iar_builtin_SEV
  325. #if !__IAR_M0_FAMILY
  326. #define __SSAT __iar_builtin_SSAT
  327. #endif
  328. #define __STREXB __iar_builtin_STREXB
  329. #define __STREXH __iar_builtin_STREXH
  330. #define __STREXW __iar_builtin_STREX
  331. #if !__IAR_M0_FAMILY
  332. #define __USAT __iar_builtin_USAT
  333. #endif
  334. #define __WFE __iar_builtin_WFE
  335. #define __WFI __iar_builtin_WFI
  336. #if __ARM_MEDIA__
  337. #define __SADD8 __iar_builtin_SADD8
  338. #define __QADD8 __iar_builtin_QADD8
  339. #define __SHADD8 __iar_builtin_SHADD8
  340. #define __UADD8 __iar_builtin_UADD8
  341. #define __UQADD8 __iar_builtin_UQADD8
  342. #define __UHADD8 __iar_builtin_UHADD8
  343. #define __SSUB8 __iar_builtin_SSUB8
  344. #define __QSUB8 __iar_builtin_QSUB8
  345. #define __SHSUB8 __iar_builtin_SHSUB8
  346. #define __USUB8 __iar_builtin_USUB8
  347. #define __UQSUB8 __iar_builtin_UQSUB8
  348. #define __UHSUB8 __iar_builtin_UHSUB8
  349. #define __SADD16 __iar_builtin_SADD16
  350. #define __QADD16 __iar_builtin_QADD16
  351. #define __SHADD16 __iar_builtin_SHADD16
  352. #define __UADD16 __iar_builtin_UADD16
  353. #define __UQADD16 __iar_builtin_UQADD16
  354. #define __UHADD16 __iar_builtin_UHADD16
  355. #define __SSUB16 __iar_builtin_SSUB16
  356. #define __QSUB16 __iar_builtin_QSUB16
  357. #define __SHSUB16 __iar_builtin_SHSUB16
  358. #define __USUB16 __iar_builtin_USUB16
  359. #define __UQSUB16 __iar_builtin_UQSUB16
  360. #define __UHSUB16 __iar_builtin_UHSUB16
  361. #define __SASX __iar_builtin_SASX
  362. #define __QASX __iar_builtin_QASX
  363. #define __SHASX __iar_builtin_SHASX
  364. #define __UASX __iar_builtin_UASX
  365. #define __UQASX __iar_builtin_UQASX
  366. #define __UHASX __iar_builtin_UHASX
  367. #define __SSAX __iar_builtin_SSAX
  368. #define __QSAX __iar_builtin_QSAX
  369. #define __SHSAX __iar_builtin_SHSAX
  370. #define __USAX __iar_builtin_USAX
  371. #define __UQSAX __iar_builtin_UQSAX
  372. #define __UHSAX __iar_builtin_UHSAX
  373. #define __USAD8 __iar_builtin_USAD8
  374. #define __USADA8 __iar_builtin_USADA8
  375. #define __SSAT16 __iar_builtin_SSAT16
  376. #define __USAT16 __iar_builtin_USAT16
  377. #define __UXTB16 __iar_builtin_UXTB16
  378. #define __UXTAB16 __iar_builtin_UXTAB16
  379. #define __SXTB16 __iar_builtin_SXTB16
  380. #define __SXTAB16 __iar_builtin_SXTAB16
  381. #define __SMUAD __iar_builtin_SMUAD
  382. #define __SMUADX __iar_builtin_SMUADX
  383. #define __SMMLA __iar_builtin_SMMLA
  384. #define __SMLAD __iar_builtin_SMLAD
  385. #define __SMLADX __iar_builtin_SMLADX
  386. #define __SMLALD __iar_builtin_SMLALD
  387. #define __SMLALDX __iar_builtin_SMLALDX
  388. #define __SMUSD __iar_builtin_SMUSD
  389. #define __SMUSDX __iar_builtin_SMUSDX
  390. #define __SMLSD __iar_builtin_SMLSD
  391. #define __SMLSDX __iar_builtin_SMLSDX
  392. #define __SMLSLD __iar_builtin_SMLSLD
  393. #define __SMLSLDX __iar_builtin_SMLSLDX
  394. #define __SEL __iar_builtin_SEL
  395. #define __QADD __iar_builtin_QADD
  396. #define __QSUB __iar_builtin_QSUB
  397. #define __PKHBT __iar_builtin_PKHBT
  398. #define __PKHTB __iar_builtin_PKHTB
  399. #endif
  400. #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
  401. #if __IAR_M0_FAMILY
  402. /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
  403. #define __CLZ __cmsis_iar_clz_not_active
  404. #define __SSAT __cmsis_iar_ssat_not_active
  405. #define __USAT __cmsis_iar_usat_not_active
  406. #define __RBIT __cmsis_iar_rbit_not_active
  407. #define __get_APSR __cmsis_iar_get_APSR_not_active
  408. #endif
  409. #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  410. (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
  411. #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
  412. #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
  413. #endif
  414. #ifdef __INTRINSICS_INCLUDED
  415. #error intrinsics.h is already included previously!
  416. #endif
  417. #include <intrinsics.h>
  418. #if __IAR_M0_FAMILY
  419. /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
  420. #undef __CLZ
  421. #undef __SSAT
  422. #undef __USAT
  423. #undef __RBIT
  424. #undef __get_APSR
  425. __STATIC_INLINE uint8_t __CLZ(uint32_t data)
  426. {
  427. if (data == 0U) { return 32U; }
  428. uint32_t count = 0U;
  429. uint32_t mask = 0x80000000U;
  430. while ((data & mask) == 0U)
  431. {
  432. count += 1U;
  433. mask = mask >> 1U;
  434. }
  435. return count;
  436. }
  437. __STATIC_INLINE uint32_t __RBIT(uint32_t v)
  438. {
  439. uint8_t sc = 31U;
  440. uint32_t r = v;
  441. for (v >>= 1U; v; v >>= 1U)
  442. {
  443. r <<= 1U;
  444. r |= v & 1U;
  445. sc--;
  446. }
  447. return (r << sc);
  448. }
  449. __STATIC_INLINE uint32_t __get_APSR(void)
  450. {
  451. uint32_t res;
  452. __asm("MRS %0,APSR" : "=r" (res));
  453. return res;
  454. }
  455. #endif
  456. #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  457. (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
  458. #undef __get_FPSCR
  459. #undef __set_FPSCR
  460. #define __get_FPSCR() (0)
  461. #define __set_FPSCR(VALUE) ((void)VALUE)
  462. #endif
  463. #pragma diag_suppress=Pe940
  464. #pragma diag_suppress=Pe177
  465. #define __enable_irq __enable_interrupt
  466. #define __disable_irq __disable_interrupt
  467. #define __NOP __no_operation
  468. #define __get_xPSR __get_PSR
  469. #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
  470. __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
  471. {
  472. return __LDREX((unsigned long *)ptr);
  473. }
  474. __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
  475. {
  476. return __STREX(value, (unsigned long *)ptr);
  477. }
  478. #endif
  479. /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  480. #if (__CORTEX_M >= 0x03)
  481. __IAR_FT uint32_t __RRX(uint32_t value)
  482. {
  483. uint32_t result;
  484. __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
  485. return(result);
  486. }
  487. __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
  488. {
  489. __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
  490. }
  491. #define __enable_fault_irq __enable_fiq
  492. #define __disable_fault_irq __disable_fiq
  493. #endif /* (__CORTEX_M >= 0x03) */
  494. __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
  495. {
  496. return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
  497. }
  498. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  499. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  500. __IAR_FT uint32_t __get_MSPLIM(void)
  501. {
  502. uint32_t res;
  503. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  504. (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
  505. // without main extensions, the non-secure MSPLIM is RAZ/WI
  506. res = 0U;
  507. #else
  508. __asm volatile("MRS %0,MSPLIM" : "=r" (res));
  509. #endif
  510. return res;
  511. }
  512. __IAR_FT void __set_MSPLIM(uint32_t value)
  513. {
  514. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  515. (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
  516. // without main extensions, the non-secure MSPLIM is RAZ/WI
  517. (void)value;
  518. #else
  519. __asm volatile("MSR MSPLIM,%0" :: "r" (value));
  520. #endif
  521. }
  522. __IAR_FT uint32_t __get_PSPLIM(void)
  523. {
  524. uint32_t res;
  525. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  526. (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
  527. // without main extensions, the non-secure PSPLIM is RAZ/WI
  528. res = 0U;
  529. #else
  530. __asm volatile("MRS %0,PSPLIM" : "=r" (res));
  531. #endif
  532. return res;
  533. }
  534. __IAR_FT void __set_PSPLIM(uint32_t value)
  535. {
  536. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  537. (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
  538. // without main extensions, the non-secure PSPLIM is RAZ/WI
  539. (void)value;
  540. #else
  541. __asm volatile("MSR PSPLIM,%0" :: "r" (value));
  542. #endif
  543. }
  544. __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
  545. {
  546. uint32_t res;
  547. __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
  548. return res;
  549. }
  550. __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
  551. {
  552. __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
  553. }
  554. __IAR_FT uint32_t __TZ_get_PSP_NS(void)
  555. {
  556. uint32_t res;
  557. __asm volatile("MRS %0,PSP_NS" : "=r" (res));
  558. return res;
  559. }
  560. __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
  561. {
  562. __asm volatile("MSR PSP_NS,%0" :: "r" (value));
  563. }
  564. __IAR_FT uint32_t __TZ_get_MSP_NS(void)
  565. {
  566. uint32_t res;
  567. __asm volatile("MRS %0,MSP_NS" : "=r" (res));
  568. return res;
  569. }
  570. __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
  571. {
  572. __asm volatile("MSR MSP_NS,%0" :: "r" (value));
  573. }
  574. __IAR_FT uint32_t __TZ_get_SP_NS(void)
  575. {
  576. uint32_t res;
  577. __asm volatile("MRS %0,SP_NS" : "=r" (res));
  578. return res;
  579. }
  580. __IAR_FT void __TZ_set_SP_NS(uint32_t value)
  581. {
  582. __asm volatile("MSR SP_NS,%0" :: "r" (value));
  583. }
  584. __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
  585. {
  586. uint32_t res;
  587. __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
  588. return res;
  589. }
  590. __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
  591. {
  592. __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
  593. }
  594. __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
  595. {
  596. uint32_t res;
  597. __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
  598. return res;
  599. }
  600. __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
  601. {
  602. __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
  603. }
  604. __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
  605. {
  606. uint32_t res;
  607. __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
  608. return res;
  609. }
  610. __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
  611. {
  612. __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
  613. }
  614. __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
  615. {
  616. uint32_t res;
  617. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  618. (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
  619. // without main extensions, the non-secure PSPLIM is RAZ/WI
  620. res = 0U;
  621. #else
  622. __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
  623. #endif
  624. return res;
  625. }
  626. __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
  627. {
  628. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  629. (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
  630. // without main extensions, the non-secure PSPLIM is RAZ/WI
  631. (void)value;
  632. #else
  633. __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
  634. #endif
  635. }
  636. __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
  637. {
  638. uint32_t res;
  639. __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
  640. return res;
  641. }
  642. __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
  643. {
  644. __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
  645. }
  646. #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
  647. #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
  648. #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
  649. #if __IAR_M0_FAMILY
  650. __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
  651. {
  652. if ((sat >= 1U) && (sat <= 32U))
  653. {
  654. const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
  655. const int32_t min = -1 - max ;
  656. if (val > max)
  657. {
  658. return max;
  659. }
  660. else if (val < min)
  661. {
  662. return min;
  663. }
  664. }
  665. return val;
  666. }
  667. __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
  668. {
  669. if (sat <= 31U)
  670. {
  671. const uint32_t max = ((1U << sat) - 1U);
  672. if (val > (int32_t)max)
  673. {
  674. return max;
  675. }
  676. else if (val < 0)
  677. {
  678. return 0U;
  679. }
  680. }
  681. return (uint32_t)val;
  682. }
  683. #endif
  684. #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  685. __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
  686. {
  687. uint32_t res;
  688. __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
  689. return ((uint8_t)res);
  690. }
  691. __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
  692. {
  693. uint32_t res;
  694. __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
  695. return ((uint16_t)res);
  696. }
  697. __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
  698. {
  699. uint32_t res;
  700. __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
  701. return res;
  702. }
  703. __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
  704. {
  705. __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
  706. }
  707. __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
  708. {
  709. __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
  710. }
  711. __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
  712. {
  713. __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
  714. }
  715. #endif /* (__CORTEX_M >= 0x03) */
  716. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  717. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  718. __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
  719. {
  720. uint32_t res;
  721. __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
  722. return ((uint8_t)res);
  723. }
  724. __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
  725. {
  726. uint32_t res;
  727. __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
  728. return ((uint16_t)res);
  729. }
  730. __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
  731. {
  732. uint32_t res;
  733. __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
  734. return res;
  735. }
  736. __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
  737. {
  738. __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
  739. }
  740. __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
  741. {
  742. __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
  743. }
  744. __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
  745. {
  746. __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
  747. }
  748. __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
  749. {
  750. uint32_t res;
  751. __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
  752. return ((uint8_t)res);
  753. }
  754. __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
  755. {
  756. uint32_t res;
  757. __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
  758. return ((uint16_t)res);
  759. }
  760. __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
  761. {
  762. uint32_t res;
  763. __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
  764. return res;
  765. }
  766. __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
  767. {
  768. uint32_t res;
  769. __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
  770. return res;
  771. }
  772. __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
  773. {
  774. uint32_t res;
  775. __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
  776. return res;
  777. }
  778. __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
  779. {
  780. uint32_t res;
  781. __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
  782. return res;
  783. }
  784. #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
  785. #undef __IAR_FT
  786. #undef __IAR_M0_FAMILY
  787. #undef __ICCARM_V8
  788. #pragma diag_default=Pe940
  789. #pragma diag_default=Pe177
  790. #endif /* __CMSIS_ICCARM_H__ */