cmsis_armcc.h 28 KB

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  1. /**************************************************************************//**
  2. * @file cmsis_armcc.h
  3. * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
  4. * @version V5.0.4
  5. * @date 10. January 2018
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. #ifndef __CMSIS_ARMCC_H
  25. #define __CMSIS_ARMCC_H
  26. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
  27. #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
  28. #endif
  29. /* CMSIS compiler control architecture macros */
  30. #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
  31. (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
  32. #define __ARM_ARCH_6M__ 1
  33. #endif
  34. #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
  35. #define __ARM_ARCH_7M__ 1
  36. #endif
  37. #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
  38. #define __ARM_ARCH_7EM__ 1
  39. #endif
  40. /* __ARM_ARCH_8M_BASE__ not applicable */
  41. /* __ARM_ARCH_8M_MAIN__ not applicable */
  42. /* CMSIS compiler specific defines */
  43. #ifndef __ASM
  44. #define __ASM __asm
  45. #endif
  46. #ifndef __INLINE
  47. #define __INLINE __inline
  48. #endif
  49. #ifndef __STATIC_INLINE
  50. #define __STATIC_INLINE static __inline
  51. #endif
  52. #ifndef __STATIC_FORCEINLINE
  53. #define __STATIC_FORCEINLINE static __forceinline
  54. #endif
  55. #ifndef __NO_RETURN
  56. #define __NO_RETURN __declspec(noreturn)
  57. #endif
  58. #ifndef __USED
  59. #define __USED __attribute__((used))
  60. #endif
  61. #ifndef __WEAK
  62. #define __WEAK __attribute__((weak))
  63. #endif
  64. #ifndef __PACKED
  65. #define __PACKED __attribute__((packed))
  66. #endif
  67. #ifndef __PACKED_STRUCT
  68. #define __PACKED_STRUCT __packed struct
  69. #endif
  70. #ifndef __PACKED_UNION
  71. #define __PACKED_UNION __packed union
  72. #endif
  73. #ifndef __UNALIGNED_UINT32 /* deprecated */
  74. #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
  75. #endif
  76. #ifndef __UNALIGNED_UINT16_WRITE
  77. #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
  78. #endif
  79. #ifndef __UNALIGNED_UINT16_READ
  80. #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
  81. #endif
  82. #ifndef __UNALIGNED_UINT32_WRITE
  83. #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
  84. #endif
  85. #ifndef __UNALIGNED_UINT32_READ
  86. #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
  87. #endif
  88. #ifndef __ALIGNED
  89. #define __ALIGNED(x) __attribute__((aligned(x)))
  90. #endif
  91. #ifndef __RESTRICT
  92. #define __RESTRICT __restrict
  93. #endif
  94. /* ########################### Core Function Access ########################### */
  95. /** \ingroup CMSIS_Core_FunctionInterface
  96. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  97. @{
  98. */
  99. /**
  100. \brief Enable IRQ Interrupts
  101. \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
  102. Can only be executed in Privileged modes.
  103. */
  104. /* intrinsic void __enable_irq(); */
  105. /**
  106. \brief Disable IRQ Interrupts
  107. \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  108. Can only be executed in Privileged modes.
  109. */
  110. /* intrinsic void __disable_irq(); */
  111. /**
  112. \brief Get Control Register
  113. \details Returns the content of the Control Register.
  114. \return Control Register value
  115. */
  116. __STATIC_INLINE uint32_t __get_CONTROL(void)
  117. {
  118. register uint32_t __regControl __ASM("control");
  119. return(__regControl);
  120. }
  121. /**
  122. \brief Set Control Register
  123. \details Writes the given value to the Control Register.
  124. \param [in] control Control Register value to set
  125. */
  126. __STATIC_INLINE void __set_CONTROL(uint32_t control)
  127. {
  128. register uint32_t __regControl __ASM("control");
  129. __regControl = control;
  130. }
  131. /**
  132. \brief Get IPSR Register
  133. \details Returns the content of the IPSR Register.
  134. \return IPSR Register value
  135. */
  136. __STATIC_INLINE uint32_t __get_IPSR(void)
  137. {
  138. register uint32_t __regIPSR __ASM("ipsr");
  139. return(__regIPSR);
  140. }
  141. /**
  142. \brief Get APSR Register
  143. \details Returns the content of the APSR Register.
  144. \return APSR Register value
  145. */
  146. __STATIC_INLINE uint32_t __get_APSR(void)
  147. {
  148. register uint32_t __regAPSR __ASM("apsr");
  149. return(__regAPSR);
  150. }
  151. /**
  152. \brief Get xPSR Register
  153. \details Returns the content of the xPSR Register.
  154. \return xPSR Register value
  155. */
  156. __STATIC_INLINE uint32_t __get_xPSR(void)
  157. {
  158. register uint32_t __regXPSR __ASM("xpsr");
  159. return(__regXPSR);
  160. }
  161. /**
  162. \brief Get Process Stack Pointer
  163. \details Returns the current value of the Process Stack Pointer (PSP).
  164. \return PSP Register value
  165. */
  166. __STATIC_INLINE uint32_t __get_PSP(void)
  167. {
  168. register uint32_t __regProcessStackPointer __ASM("psp");
  169. return(__regProcessStackPointer);
  170. }
  171. /**
  172. \brief Set Process Stack Pointer
  173. \details Assigns the given value to the Process Stack Pointer (PSP).
  174. \param [in] topOfProcStack Process Stack Pointer value to set
  175. */
  176. __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  177. {
  178. register uint32_t __regProcessStackPointer __ASM("psp");
  179. __regProcessStackPointer = topOfProcStack;
  180. }
  181. /**
  182. \brief Get Main Stack Pointer
  183. \details Returns the current value of the Main Stack Pointer (MSP).
  184. \return MSP Register value
  185. */
  186. __STATIC_INLINE uint32_t __get_MSP(void)
  187. {
  188. register uint32_t __regMainStackPointer __ASM("msp");
  189. return(__regMainStackPointer);
  190. }
  191. /**
  192. \brief Set Main Stack Pointer
  193. \details Assigns the given value to the Main Stack Pointer (MSP).
  194. \param [in] topOfMainStack Main Stack Pointer value to set
  195. */
  196. __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  197. {
  198. register uint32_t __regMainStackPointer __ASM("msp");
  199. __regMainStackPointer = topOfMainStack;
  200. }
  201. /**
  202. \brief Get Priority Mask
  203. \details Returns the current state of the priority mask bit from the Priority Mask Register.
  204. \return Priority Mask value
  205. */
  206. __STATIC_INLINE uint32_t __get_PRIMASK(void)
  207. {
  208. register uint32_t __regPriMask __ASM("primask");
  209. return(__regPriMask);
  210. }
  211. /**
  212. \brief Set Priority Mask
  213. \details Assigns the given value to the Priority Mask Register.
  214. \param [in] priMask Priority Mask
  215. */
  216. __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  217. {
  218. register uint32_t __regPriMask __ASM("primask");
  219. __regPriMask = (priMask);
  220. }
  221. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  222. (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
  223. /**
  224. \brief Enable FIQ
  225. \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
  226. Can only be executed in Privileged modes.
  227. */
  228. #define __enable_fault_irq __enable_fiq
  229. /**
  230. \brief Disable FIQ
  231. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
  232. Can only be executed in Privileged modes.
  233. */
  234. #define __disable_fault_irq __disable_fiq
  235. /**
  236. \brief Get Base Priority
  237. \details Returns the current value of the Base Priority register.
  238. \return Base Priority register value
  239. */
  240. __STATIC_INLINE uint32_t __get_BASEPRI(void)
  241. {
  242. register uint32_t __regBasePri __ASM("basepri");
  243. return(__regBasePri);
  244. }
  245. /**
  246. \brief Set Base Priority
  247. \details Assigns the given value to the Base Priority register.
  248. \param [in] basePri Base Priority value to set
  249. */
  250. __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  251. {
  252. register uint32_t __regBasePri __ASM("basepri");
  253. __regBasePri = (basePri & 0xFFU);
  254. }
  255. /**
  256. \brief Set Base Priority with condition
  257. \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
  258. or the new value increases the BASEPRI priority level.
  259. \param [in] basePri Base Priority value to set
  260. */
  261. __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
  262. {
  263. register uint32_t __regBasePriMax __ASM("basepri_max");
  264. __regBasePriMax = (basePri & 0xFFU);
  265. }
  266. /**
  267. \brief Get Fault Mask
  268. \details Returns the current value of the Fault Mask register.
  269. \return Fault Mask register value
  270. */
  271. __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  272. {
  273. register uint32_t __regFaultMask __ASM("faultmask");
  274. return(__regFaultMask);
  275. }
  276. /**
  277. \brief Set Fault Mask
  278. \details Assigns the given value to the Fault Mask register.
  279. \param [in] faultMask Fault Mask value to set
  280. */
  281. __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  282. {
  283. register uint32_t __regFaultMask __ASM("faultmask");
  284. __regFaultMask = (faultMask & (uint32_t)1U);
  285. }
  286. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  287. (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
  288. /**
  289. \brief Get FPSCR
  290. \details Returns the current value of the Floating Point Status/Control register.
  291. \return Floating Point Status/Control register value
  292. */
  293. __STATIC_INLINE uint32_t __get_FPSCR(void)
  294. {
  295. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  296. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  297. register uint32_t __regfpscr __ASM("fpscr");
  298. return(__regfpscr);
  299. #else
  300. return(0U);
  301. #endif
  302. }
  303. /**
  304. \brief Set FPSCR
  305. \details Assigns the given value to the Floating Point Status/Control register.
  306. \param [in] fpscr Floating Point Status/Control value to set
  307. */
  308. __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  309. {
  310. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  311. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  312. register uint32_t __regfpscr __ASM("fpscr");
  313. __regfpscr = (fpscr);
  314. #else
  315. (void)fpscr;
  316. #endif
  317. }
  318. /*@} end of CMSIS_Core_RegAccFunctions */
  319. /* ########################## Core Instruction Access ######################### */
  320. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  321. Access to dedicated instructions
  322. @{
  323. */
  324. /**
  325. \brief No Operation
  326. \details No Operation does nothing. This instruction can be used for code alignment purposes.
  327. */
  328. #define __NOP __nop
  329. /**
  330. \brief Wait For Interrupt
  331. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  332. */
  333. #define __WFI __wfi
  334. /**
  335. \brief Wait For Event
  336. \details Wait For Event is a hint instruction that permits the processor to enter
  337. a low-power state until one of a number of events occurs.
  338. */
  339. #define __WFE __wfe
  340. /**
  341. \brief Send Event
  342. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  343. */
  344. #define __SEV __sev
  345. /**
  346. \brief Instruction Synchronization Barrier
  347. \details Instruction Synchronization Barrier flushes the pipeline in the processor,
  348. so that all instructions following the ISB are fetched from cache or memory,
  349. after the instruction has been completed.
  350. */
  351. #define __ISB() do {\
  352. __schedule_barrier();\
  353. __isb(0xF);\
  354. __schedule_barrier();\
  355. } while (0U)
  356. /**
  357. \brief Data Synchronization Barrier
  358. \details Acts as a special kind of Data Memory Barrier.
  359. It completes when all explicit memory accesses before this instruction complete.
  360. */
  361. #define __DSB() do {\
  362. __schedule_barrier();\
  363. __dsb(0xF);\
  364. __schedule_barrier();\
  365. } while (0U)
  366. /**
  367. \brief Data Memory Barrier
  368. \details Ensures the apparent order of the explicit memory operations before
  369. and after the instruction, without ensuring their completion.
  370. */
  371. #define __DMB() do {\
  372. __schedule_barrier();\
  373. __dmb(0xF);\
  374. __schedule_barrier();\
  375. } while (0U)
  376. /**
  377. \brief Reverse byte order (32 bit)
  378. \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  379. \param [in] value Value to reverse
  380. \return Reversed value
  381. */
  382. #define __REV __rev
  383. /**
  384. \brief Reverse byte order (16 bit)
  385. \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  386. \param [in] value Value to reverse
  387. \return Reversed value
  388. */
  389. #ifndef __NO_EMBEDDED_ASM
  390. __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
  391. {
  392. rev16 r0, r0
  393. bx lr
  394. }
  395. #endif
  396. /**
  397. \brief Reverse byte order (16 bit)
  398. \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  399. \param [in] value Value to reverse
  400. \return Reversed value
  401. */
  402. #ifndef __NO_EMBEDDED_ASM
  403. __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
  404. {
  405. revsh r0, r0
  406. bx lr
  407. }
  408. #endif
  409. /**
  410. \brief Rotate Right in unsigned value (32 bit)
  411. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  412. \param [in] op1 Value to rotate
  413. \param [in] op2 Number of Bits to rotate
  414. \return Rotated value
  415. */
  416. #define __ROR __ror
  417. /**
  418. \brief Breakpoint
  419. \details Causes the processor to enter Debug state.
  420. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  421. \param [in] value is ignored by the processor.
  422. If required, a debugger can use it to store additional information about the breakpoint.
  423. */
  424. #define __BKPT(value) __breakpoint(value)
  425. /**
  426. \brief Reverse bit order of value
  427. \details Reverses the bit order of the given value.
  428. \param [in] value Value to reverse
  429. \return Reversed value
  430. */
  431. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  432. (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
  433. #define __RBIT __rbit
  434. #else
  435. __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  436. {
  437. uint32_t result;
  438. uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
  439. result = value; /* r will be reversed bits of v; first get LSB of v */
  440. for (value >>= 1U; value != 0U; value >>= 1U)
  441. {
  442. result <<= 1U;
  443. result |= value & 1U;
  444. s--;
  445. }
  446. result <<= s; /* shift when v's highest bits are zero */
  447. return result;
  448. }
  449. #endif
  450. /**
  451. \brief Count leading zeros
  452. \details Counts the number of leading zeros of a data value.
  453. \param [in] value Value to count the leading zeros
  454. \return number of leading zeros in value
  455. */
  456. #define __CLZ __clz
  457. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  458. (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
  459. /**
  460. \brief LDR Exclusive (8 bit)
  461. \details Executes a exclusive LDR instruction for 8 bit value.
  462. \param [in] ptr Pointer to data
  463. \return value of type uint8_t at (*ptr)
  464. */
  465. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  466. #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
  467. #else
  468. #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
  469. #endif
  470. /**
  471. \brief LDR Exclusive (16 bit)
  472. \details Executes a exclusive LDR instruction for 16 bit values.
  473. \param [in] ptr Pointer to data
  474. \return value of type uint16_t at (*ptr)
  475. */
  476. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  477. #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
  478. #else
  479. #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
  480. #endif
  481. /**
  482. \brief LDR Exclusive (32 bit)
  483. \details Executes a exclusive LDR instruction for 32 bit values.
  484. \param [in] ptr Pointer to data
  485. \return value of type uint32_t at (*ptr)
  486. */
  487. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  488. #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
  489. #else
  490. #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
  491. #endif
  492. /**
  493. \brief STR Exclusive (8 bit)
  494. \details Executes a exclusive STR instruction for 8 bit values.
  495. \param [in] value Value to store
  496. \param [in] ptr Pointer to location
  497. \return 0 Function succeeded
  498. \return 1 Function failed
  499. */
  500. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  501. #define __STREXB(value, ptr) __strex(value, ptr)
  502. #else
  503. #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
  504. #endif
  505. /**
  506. \brief STR Exclusive (16 bit)
  507. \details Executes a exclusive STR instruction for 16 bit values.
  508. \param [in] value Value to store
  509. \param [in] ptr Pointer to location
  510. \return 0 Function succeeded
  511. \return 1 Function failed
  512. */
  513. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  514. #define __STREXH(value, ptr) __strex(value, ptr)
  515. #else
  516. #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
  517. #endif
  518. /**
  519. \brief STR Exclusive (32 bit)
  520. \details Executes a exclusive STR instruction for 32 bit values.
  521. \param [in] value Value to store
  522. \param [in] ptr Pointer to location
  523. \return 0 Function succeeded
  524. \return 1 Function failed
  525. */
  526. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  527. #define __STREXW(value, ptr) __strex(value, ptr)
  528. #else
  529. #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
  530. #endif
  531. /**
  532. \brief Remove the exclusive lock
  533. \details Removes the exclusive lock which is created by LDREX.
  534. */
  535. #define __CLREX __clrex
  536. /**
  537. \brief Signed Saturate
  538. \details Saturates a signed value.
  539. \param [in] value Value to be saturated
  540. \param [in] sat Bit position to saturate to (1..32)
  541. \return Saturated value
  542. */
  543. #define __SSAT __ssat
  544. /**
  545. \brief Unsigned Saturate
  546. \details Saturates an unsigned value.
  547. \param [in] value Value to be saturated
  548. \param [in] sat Bit position to saturate to (0..31)
  549. \return Saturated value
  550. */
  551. #define __USAT __usat
  552. /**
  553. \brief Rotate Right with Extend (32 bit)
  554. \details Moves each bit of a bitstring right by one bit.
  555. The carry input is shifted in at the left end of the bitstring.
  556. \param [in] value Value to rotate
  557. \return Rotated value
  558. */
  559. #ifndef __NO_EMBEDDED_ASM
  560. __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
  561. {
  562. rrx r0, r0
  563. bx lr
  564. }
  565. #endif
  566. /**
  567. \brief LDRT Unprivileged (8 bit)
  568. \details Executes a Unprivileged LDRT instruction for 8 bit value.
  569. \param [in] ptr Pointer to data
  570. \return value of type uint8_t at (*ptr)
  571. */
  572. #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
  573. /**
  574. \brief LDRT Unprivileged (16 bit)
  575. \details Executes a Unprivileged LDRT instruction for 16 bit values.
  576. \param [in] ptr Pointer to data
  577. \return value of type uint16_t at (*ptr)
  578. */
  579. #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
  580. /**
  581. \brief LDRT Unprivileged (32 bit)
  582. \details Executes a Unprivileged LDRT instruction for 32 bit values.
  583. \param [in] ptr Pointer to data
  584. \return value of type uint32_t at (*ptr)
  585. */
  586. #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
  587. /**
  588. \brief STRT Unprivileged (8 bit)
  589. \details Executes a Unprivileged STRT instruction for 8 bit values.
  590. \param [in] value Value to store
  591. \param [in] ptr Pointer to location
  592. */
  593. #define __STRBT(value, ptr) __strt(value, ptr)
  594. /**
  595. \brief STRT Unprivileged (16 bit)
  596. \details Executes a Unprivileged STRT instruction for 16 bit values.
  597. \param [in] value Value to store
  598. \param [in] ptr Pointer to location
  599. */
  600. #define __STRHT(value, ptr) __strt(value, ptr)
  601. /**
  602. \brief STRT Unprivileged (32 bit)
  603. \details Executes a Unprivileged STRT instruction for 32 bit values.
  604. \param [in] value Value to store
  605. \param [in] ptr Pointer to location
  606. */
  607. #define __STRT(value, ptr) __strt(value, ptr)
  608. #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  609. (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
  610. /**
  611. \brief Signed Saturate
  612. \details Saturates a signed value.
  613. \param [in] value Value to be saturated
  614. \param [in] sat Bit position to saturate to (1..32)
  615. \return Saturated value
  616. */
  617. __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
  618. {
  619. if ((sat >= 1U) && (sat <= 32U))
  620. {
  621. const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
  622. const int32_t min = -1 - max ;
  623. if (val > max)
  624. {
  625. return max;
  626. }
  627. else if (val < min)
  628. {
  629. return min;
  630. }
  631. }
  632. return val;
  633. }
  634. /**
  635. \brief Unsigned Saturate
  636. \details Saturates an unsigned value.
  637. \param [in] value Value to be saturated
  638. \param [in] sat Bit position to saturate to (0..31)
  639. \return Saturated value
  640. */
  641. __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
  642. {
  643. if (sat <= 31U)
  644. {
  645. const uint32_t max = ((1U << sat) - 1U);
  646. if (val > (int32_t)max)
  647. {
  648. return max;
  649. }
  650. else if (val < 0)
  651. {
  652. return 0U;
  653. }
  654. }
  655. return (uint32_t)val;
  656. }
  657. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  658. (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
  659. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
  660. /* ################### Compiler specific Intrinsics ########################### */
  661. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  662. Access to dedicated SIMD instructions
  663. @{
  664. */
  665. #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
  666. #define __SADD8 __sadd8
  667. #define __QADD8 __qadd8
  668. #define __SHADD8 __shadd8
  669. #define __UADD8 __uadd8
  670. #define __UQADD8 __uqadd8
  671. #define __UHADD8 __uhadd8
  672. #define __SSUB8 __ssub8
  673. #define __QSUB8 __qsub8
  674. #define __SHSUB8 __shsub8
  675. #define __USUB8 __usub8
  676. #define __UQSUB8 __uqsub8
  677. #define __UHSUB8 __uhsub8
  678. #define __SADD16 __sadd16
  679. #define __QADD16 __qadd16
  680. #define __SHADD16 __shadd16
  681. #define __UADD16 __uadd16
  682. #define __UQADD16 __uqadd16
  683. #define __UHADD16 __uhadd16
  684. #define __SSUB16 __ssub16
  685. #define __QSUB16 __qsub16
  686. #define __SHSUB16 __shsub16
  687. #define __USUB16 __usub16
  688. #define __UQSUB16 __uqsub16
  689. #define __UHSUB16 __uhsub16
  690. #define __SASX __sasx
  691. #define __QASX __qasx
  692. #define __SHASX __shasx
  693. #define __UASX __uasx
  694. #define __UQASX __uqasx
  695. #define __UHASX __uhasx
  696. #define __SSAX __ssax
  697. #define __QSAX __qsax
  698. #define __SHSAX __shsax
  699. #define __USAX __usax
  700. #define __UQSAX __uqsax
  701. #define __UHSAX __uhsax
  702. #define __USAD8 __usad8
  703. #define __USADA8 __usada8
  704. #define __SSAT16 __ssat16
  705. #define __USAT16 __usat16
  706. #define __UXTB16 __uxtb16
  707. #define __UXTAB16 __uxtab16
  708. #define __SXTB16 __sxtb16
  709. #define __SXTAB16 __sxtab16
  710. #define __SMUAD __smuad
  711. #define __SMUADX __smuadx
  712. #define __SMLAD __smlad
  713. #define __SMLADX __smladx
  714. #define __SMLALD __smlald
  715. #define __SMLALDX __smlaldx
  716. #define __SMUSD __smusd
  717. #define __SMUSDX __smusdx
  718. #define __SMLSD __smlsd
  719. #define __SMLSDX __smlsdx
  720. #define __SMLSLD __smlsld
  721. #define __SMLSLDX __smlsldx
  722. #define __SEL __sel
  723. #define __QADD __qadd
  724. #define __QSUB __qsub
  725. #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
  726. ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
  727. #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
  728. ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
  729. #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
  730. ((int64_t)(ARG3) << 32U) ) >> 32U))
  731. #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
  732. /*@} end of group CMSIS_SIMD_intrinsics */
  733. #endif /* __CMSIS_ARMCC_H */