system_stm32f1xx.c 15 KB

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  1. /**
  2. ******************************************************************************
  3. * @file system_stm32f1xx.c
  4. * @author MCD Application Team
  5. * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
  6. *
  7. * 1. This file provides two functions and one global variable to be called from
  8. * user application:
  9. * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  10. * factors, AHB/APBx prescalers and Flash settings).
  11. * This function is called at startup just after reset and
  12. * before branch to main program. This call is made inside
  13. * the "startup_stm32f1xx_xx.s" file.
  14. *
  15. * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16. * by the user application to setup the SysTick
  17. * timer or configure other parameters.
  18. *
  19. * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20. * be called whenever the core clock is changed
  21. * during program execution.
  22. *
  23. * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24. * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
  25. * configure the system clock before to branch to main program.
  26. *
  27. * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
  28. * the product used), refer to "HSE_VALUE".
  29. * When HSE is used as system clock source, directly or through PLL, and you
  30. * are using different crystal you have to adapt the HSE value to your own
  31. * configuration.
  32. *
  33. ******************************************************************************
  34. * @attention
  35. *
  36. * Copyright (c) 2017-2021 STMicroelectronics.
  37. * All rights reserved.
  38. *
  39. * This software is licensed under terms that can be found in the LICENSE file
  40. * in the root directory of this software component.
  41. * If no LICENSE file comes with this software, it is provided AS-IS.
  42. *
  43. ******************************************************************************
  44. */
  45. /** @addtogroup CMSIS
  46. * @{
  47. */
  48. /** @addtogroup stm32f1xx_system
  49. * @{
  50. */
  51. /** @addtogroup STM32F1xx_System_Private_Includes
  52. * @{
  53. */
  54. #include "stm32f1xx.h"
  55. /**
  56. * @}
  57. */
  58. /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
  59. * @{
  60. */
  61. /**
  62. * @}
  63. */
  64. /** @addtogroup STM32F1xx_System_Private_Defines
  65. * @{
  66. */
  67. #if !defined(HSE_VALUE)
  68. #define HSE_VALUE \
  69. 8000000U /*!< Default value of the External oscillator in Hz. \
  70. This value can be provided and adapted by the user application. */
  71. #endif /* HSE_VALUE */
  72. #if !defined(HSI_VALUE)
  73. #define HSI_VALUE \
  74. 8000000U /*!< Default value of the Internal oscillator in Hz. \
  75. This value can be provided and adapted by the user application. */
  76. #endif /* HSI_VALUE */
  77. /*!< Uncomment the following line if you need to use external SRAM */
  78. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || \
  79. defined(STM32F103xE) || defined(STM32F103xG)
  80. /* #define DATA_IN_ExtSRAM */
  81. #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
  82. /* Note: Following vector table addresses must be defined in line with linker
  83. configuration. */
  84. /*!< Uncomment the following line if you need to relocate the vector table
  85. anywhere in Flash or Sram, else the vector table is kept at the automatic
  86. remap of boot address selected */
  87. /* #define USER_VECT_TAB_ADDRESS */
  88. #if defined(USER_VECT_TAB_ADDRESS)
  89. /*!< Uncomment the following line if you need to relocate your vector Table
  90. in Sram else user remap will be done in Flash. */
  91. /* #define VECT_TAB_SRAM */
  92. #if defined(VECT_TAB_SRAM)
  93. #define VECT_TAB_BASE_ADDRESS \
  94. SRAM_BASE /*!< Vector Table base address field. \
  95. This value must be a multiple of 0x200. */
  96. #define VECT_TAB_OFFSET \
  97. 0x00000000U /*!< Vector Table base offset field. \
  98. This value must be a multiple of 0x200. */
  99. #else
  100. #define VECT_TAB_BASE_ADDRESS \
  101. FLASH_BASE /*!< Vector Table base address field. \
  102. This value must be a multiple of 0x200. */
  103. #define VECT_TAB_OFFSET \
  104. 0x00000000U /*!< Vector Table base offset field. \
  105. This value must be a multiple of 0x200. */
  106. #endif /* VECT_TAB_SRAM */
  107. #endif /* USER_VECT_TAB_ADDRESS */
  108. /******************************************************************************/
  109. /**
  110. * @}
  111. */
  112. /** @addtogroup STM32F1xx_System_Private_Macros
  113. * @{
  114. */
  115. /**
  116. * @}
  117. */
  118. /** @addtogroup STM32F1xx_System_Private_Variables
  119. * @{
  120. */
  121. /* This variable is updated in three ways:
  122. 1) by calling CMSIS function SystemCoreClockUpdate()
  123. 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
  124. 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
  125. Note: If you use this function to configure the system clock; then there
  126. is no need to call the 2 first functions listed above, since SystemCoreClock
  127. variable is updated automatically.
  128. */
  129. uint32_t SystemCoreClock = 16000000;
  130. const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  131. const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
  132. /**
  133. * @}
  134. */
  135. /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
  136. * @{
  137. */
  138. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || \
  139. defined(STM32F103xE) || defined(STM32F103xG)
  140. #ifdef DATA_IN_ExtSRAM
  141. static void SystemInit_ExtMemCtl(void);
  142. #endif /* DATA_IN_ExtSRAM */
  143. #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
  144. /**
  145. * @}
  146. */
  147. /** @addtogroup STM32F1xx_System_Private_Functions
  148. * @{
  149. */
  150. /**
  151. * @brief Setup the microcontroller system
  152. * Initialize the Embedded Flash Interface, the PLL and update the
  153. * SystemCoreClock variable.
  154. * @note This function should be used only after reset.
  155. * @param None
  156. * @retval None
  157. */
  158. void SystemInit(void)
  159. {
  160. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || \
  161. defined(STM32F103xE) || defined(STM32F103xG)
  162. #ifdef DATA_IN_ExtSRAM
  163. SystemInit_ExtMemCtl();
  164. #endif /* DATA_IN_ExtSRAM */
  165. #endif
  166. /* Configure the Vector Table location -------------------------------------*/
  167. #if defined(USER_VECT_TAB_ADDRESS)
  168. SCB->VTOR =
  169. VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
  170. #endif /* USER_VECT_TAB_ADDRESS */
  171. }
  172. /**
  173. * @brief Update SystemCoreClock variable according to Clock Register Values.
  174. * The SystemCoreClock variable contains the core clock (HCLK), it can
  175. * be used by the user application to setup the SysTick timer or configure
  176. * other parameters.
  177. *
  178. * @note Each time the core clock (HCLK) changes, this function must be called
  179. * to update SystemCoreClock variable value. Otherwise, any configuration
  180. * based on this variable will be incorrect.
  181. *
  182. * @note - The system frequency computed by this function is not the real
  183. * frequency in the chip. It is calculated based on the predefined
  184. * constant and the selected clock source:
  185. *
  186. * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  187. *
  188. * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  189. *
  190. * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  191. * or HSI_VALUE(*) multiplied by the PLL factors.
  192. *
  193. * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
  194. * 8 MHz) but the real value may vary depending on the variations
  195. * in voltage and temperature.
  196. *
  197. * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
  198. * 8 MHz or 25 MHz, depending on the product used), user has to ensure
  199. * that HSE_VALUE is same as the real frequency of the crystal used.
  200. * Otherwise, this function may have wrong result.
  201. *
  202. * - The result of this function could be not correct when using fractional
  203. * value for HSE crystal.
  204. * @param None
  205. * @retval None
  206. */
  207. void SystemCoreClockUpdate(void)
  208. {
  209. uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
  210. #if defined(STM32F105xC) || defined(STM32F107xC)
  211. uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
  212. #endif /* STM32F105xC */
  213. #if defined(STM32F100xB) || defined(STM32F100xE)
  214. uint32_t prediv1factor = 0U;
  215. #endif /* STM32F100xB or STM32F100xE */
  216. /* Get SYSCLK source -------------------------------------------------------*/
  217. tmp = RCC->CFGR & RCC_CFGR_SWS;
  218. switch (tmp)
  219. {
  220. case 0x00U: /* HSI used as system clock */
  221. SystemCoreClock = HSI_VALUE;
  222. break;
  223. case 0x04U: /* HSE used as system clock */
  224. SystemCoreClock = HSE_VALUE;
  225. break;
  226. case 0x08U: /* PLL used as system clock */
  227. /* Get PLL clock source and multiplication factor ----------------------*/
  228. pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
  229. pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
  230. #if !defined(STM32F105xC) && !defined(STM32F107xC)
  231. pllmull = (pllmull >> 18U) + 2U;
  232. if (pllsource == 0x00U)
  233. {
  234. /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  235. SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
  236. }
  237. else
  238. {
  239. #if defined(STM32F100xB) || defined(STM32F100xE)
  240. prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
  241. /* HSE oscillator clock selected as PREDIV1 clock entry */
  242. SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
  243. #else
  244. /* HSE selected as PLL clock entry */
  245. if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
  246. { /* HSE oscillator clock divided by 2 */
  247. SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
  248. }
  249. else
  250. {
  251. SystemCoreClock = HSE_VALUE * pllmull;
  252. }
  253. #endif
  254. }
  255. #else
  256. pllmull = pllmull >> 18U;
  257. if (pllmull != 0x0DU)
  258. {
  259. pllmull += 2U;
  260. }
  261. else
  262. { /* PLL multiplication factor = PLL input clock * 6.5 */
  263. pllmull = 13U / 2U;
  264. }
  265. if (pllsource == 0x00U)
  266. {
  267. /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  268. SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
  269. }
  270. else
  271. { /* PREDIV1 selected as PLL clock entry */
  272. /* Get PREDIV1 clock source and division factor */
  273. prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
  274. prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
  275. if (prediv1source == 0U)
  276. {
  277. /* HSE oscillator clock selected as PREDIV1 clock entry */
  278. SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
  279. }
  280. else
  281. { /* PLL2 clock selected as PREDIV1 clock entry */
  282. /* Get PREDIV2 division factor and PLL2 multiplication factor */
  283. prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
  284. pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
  285. SystemCoreClock =
  286. (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
  287. }
  288. }
  289. #endif /* STM32F105xC */
  290. break;
  291. default:
  292. SystemCoreClock = HSI_VALUE;
  293. break;
  294. }
  295. /* Compute HCLK clock frequency ----------------*/
  296. /* Get HCLK prescaler */
  297. tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
  298. /* HCLK clock frequency */
  299. SystemCoreClock >>= tmp;
  300. }
  301. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || \
  302. defined(STM32F103xE) || defined(STM32F103xG)
  303. /**
  304. * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
  305. * before jump to __main
  306. * @param None
  307. * @retval None
  308. */
  309. #ifdef DATA_IN_ExtSRAM
  310. /**
  311. * @brief Setup the external memory controller.
  312. * Called in startup_stm32f1xx_xx.s/.c before jump to main.
  313. * This function configures the external SRAM mounted on STM3210E-EVAL
  314. * board (STM32 High density devices). This SRAM will be used as program
  315. * data memory (including heap and stack).
  316. * @param None
  317. * @retval None
  318. */
  319. void SystemInit_ExtMemCtl(void)
  320. {
  321. __IO uint32_t tmpreg;
  322. /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
  323. required, then adjust the Register Addresses */
  324. /* Enable FSMC clock */
  325. RCC->AHBENR = 0x00000114U;
  326. /* Delay after an RCC peripheral clock enabling */
  327. tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
  328. /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
  329. RCC->APB2ENR = 0x000001E0U;
  330. /* Delay after an RCC peripheral clock enabling */
  331. tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
  332. (void)(tmpreg);
  333. /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
  334. /*---------------- SRAM Address lines configuration -------------------------*/
  335. /*---------------- NOE and NWE configuration --------------------------------*/
  336. /*---------------- NE3 configuration ----------------------------------------*/
  337. /*---------------- NBL0, NBL1 configuration ---------------------------------*/
  338. GPIOD->CRL = 0x44BB44BBU;
  339. GPIOD->CRH = 0xBBBBBBBBU;
  340. GPIOE->CRL = 0xB44444BBU;
  341. GPIOE->CRH = 0xBBBBBBBBU;
  342. GPIOF->CRL = 0x44BBBBBBU;
  343. GPIOF->CRH = 0xBBBB4444U;
  344. GPIOG->CRL = 0x44BBBBBBU;
  345. GPIOG->CRH = 0x444B4B44U;
  346. /*---------------- FSMC Configuration ---------------------------------------*/
  347. /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
  348. FSMC_Bank1->BTCR[4U] = 0x00001091U;
  349. FSMC_Bank1->BTCR[5U] = 0x00110212U;
  350. }
  351. #endif /* DATA_IN_ExtSRAM */
  352. #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
  353. /**
  354. * @}
  355. */
  356. /**
  357. * @}
  358. */
  359. /**
  360. * @}
  361. */