stm32f1xx_hal_sram.c 33 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_hal_sram.c
  4. * @author MCD Application Team
  5. * @brief SRAM HAL module driver.
  6. * This file provides a generic firmware to drive SRAM memories
  7. * mounted as external device.
  8. *
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * Copyright (c) 2016 STMicroelectronics.
  13. * All rights reserved.
  14. *
  15. * This software is licensed under terms that can be found in the LICENSE file
  16. * in the root directory of this software component.
  17. * If no LICENSE file comes with this software, it is provided AS-IS.
  18. *
  19. ******************************************************************************
  20. @verbatim
  21. ==============================================================================
  22. ##### How to use this driver #####
  23. ==============================================================================
  24. [..]
  25. This driver is a generic layered driver which contains a set of APIs used to
  26. control SRAM memories. It uses the FSMC layer functions to interface
  27. with SRAM devices.
  28. The following sequence should be followed to configure the FSMC to interface
  29. with SRAM/PSRAM memories:
  30. (#) Declare a SRAM_HandleTypeDef handle structure, for example:
  31. SRAM_HandleTypeDef hsram; and:
  32. (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
  33. values of the structure member.
  34. (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
  35. base register instance for NOR or SRAM device
  36. (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
  37. base register instance for NOR or SRAM extended mode
  38. (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
  39. mode timings; for example:
  40. FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
  41. and fill its fields with the allowed values of the structure member.
  42. (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
  43. performs the following sequence:
  44. (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
  45. (##) Control register configuration using the FSMC NORSRAM interface function
  46. FSMC_NORSRAM_Init()
  47. (##) Timing register configuration using the FSMC NORSRAM interface function
  48. FSMC_NORSRAM_Timing_Init()
  49. (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
  50. FSMC_NORSRAM_Extended_Timing_Init()
  51. (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
  52. (#) At this stage you can perform read/write accesses from/to the memory connected
  53. to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
  54. following APIs:
  55. (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
  56. (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
  57. (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
  58. HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
  59. (#) You can continuously monitor the SRAM device HAL state by calling the function
  60. HAL_SRAM_GetState()
  61. *** Callback registration ***
  62. =============================================
  63. [..]
  64. The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
  65. allows the user to configure dynamically the driver callbacks.
  66. Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
  67. it allows to register following callbacks:
  68. (+) MspInitCallback : SRAM MspInit.
  69. (+) MspDeInitCallback : SRAM MspDeInit.
  70. This function takes as parameters the HAL peripheral handle, the Callback ID
  71. and a pointer to the user callback function.
  72. Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
  73. weak (overridden) function. It allows to reset following callbacks:
  74. (+) MspInitCallback : SRAM MspInit.
  75. (+) MspDeInitCallback : SRAM MspDeInit.
  76. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  77. By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
  78. all callbacks are reset to the corresponding legacy weak (overridden) functions.
  79. Exception done for MspInit and MspDeInit callbacks that are respectively
  80. reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
  81. and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
  82. If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
  83. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  84. Callbacks can be registered/unregistered in READY state only.
  85. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  86. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  87. during the Init/DeInit.
  88. In that case first register the MspInit/MspDeInit user callbacks
  89. using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
  90. or HAL_SRAM_Init function.
  91. When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
  92. not defined, the callback registering feature is not available
  93. and weak (overridden) callbacks are used.
  94. @endverbatim
  95. ******************************************************************************
  96. */
  97. /* Includes ------------------------------------------------------------------*/
  98. #include "stm32f1xx_hal.h"
  99. #if defined(FSMC_BANK1)
  100. /** @addtogroup STM32F1xx_HAL_Driver
  101. * @{
  102. */
  103. #ifdef HAL_SRAM_MODULE_ENABLED
  104. /** @defgroup SRAM SRAM
  105. * @brief SRAM driver modules
  106. * @{
  107. */
  108. /* Private typedef -----------------------------------------------------------*/
  109. /* Private define ------------------------------------------------------------*/
  110. /* Private macro -------------------------------------------------------------*/
  111. /* Private variables ---------------------------------------------------------*/
  112. /* Private function prototypes -----------------------------------------------*/
  113. /** @addtogroup SRAM_Private_Functions SRAM Private Functions
  114. * @{
  115. */
  116. static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
  117. static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
  118. static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
  119. /**
  120. * @}
  121. */
  122. /* Exported functions --------------------------------------------------------*/
  123. /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
  124. * @{
  125. */
  126. /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  127. * @brief Initialization and Configuration functions.
  128. *
  129. @verbatim
  130. ==============================================================================
  131. ##### SRAM Initialization and de_initialization functions #####
  132. ==============================================================================
  133. [..] This section provides functions allowing to initialize/de-initialize
  134. the SRAM memory
  135. @endverbatim
  136. * @{
  137. */
  138. /**
  139. * @brief Performs the SRAM device initialization sequence
  140. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  141. * the configuration information for SRAM module.
  142. * @param Timing Pointer to SRAM control timing structure
  143. * @param ExtTiming Pointer to SRAM extended mode timing structure
  144. * @retval HAL status
  145. */
  146. HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
  147. FSMC_NORSRAM_TimingTypeDef *ExtTiming)
  148. {
  149. /* Check the SRAM handle parameter */
  150. if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
  151. {
  152. return HAL_ERROR;
  153. }
  154. if (hsram->State == HAL_SRAM_STATE_RESET)
  155. {
  156. /* Allocate lock resource and initialize it */
  157. hsram->Lock = HAL_UNLOCKED;
  158. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  159. if (hsram->MspInitCallback == NULL)
  160. {
  161. hsram->MspInitCallback = HAL_SRAM_MspInit;
  162. }
  163. hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
  164. hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
  165. /* Init the low level hardware */
  166. hsram->MspInitCallback(hsram);
  167. #else
  168. /* Initialize the low level hardware (MSP) */
  169. HAL_SRAM_MspInit(hsram);
  170. #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
  171. }
  172. /* Initialize SRAM control Interface */
  173. (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
  174. /* Initialize SRAM timing Interface */
  175. (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
  176. /* Initialize SRAM extended mode timing Interface */
  177. (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
  178. hsram->Init.ExtendedMode);
  179. /* Enable the NORSRAM device */
  180. __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
  181. /* Initialize the SRAM controller state */
  182. hsram->State = HAL_SRAM_STATE_READY;
  183. return HAL_OK;
  184. }
  185. /**
  186. * @brief Performs the SRAM device De-initialization sequence.
  187. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  188. * the configuration information for SRAM module.
  189. * @retval HAL status
  190. */
  191. HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
  192. {
  193. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  194. if (hsram->MspDeInitCallback == NULL)
  195. {
  196. hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
  197. }
  198. /* DeInit the low level hardware */
  199. hsram->MspDeInitCallback(hsram);
  200. #else
  201. /* De-Initialize the low level hardware (MSP) */
  202. HAL_SRAM_MspDeInit(hsram);
  203. #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
  204. /* Configure the SRAM registers with their reset values */
  205. (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
  206. /* Reset the SRAM controller state */
  207. hsram->State = HAL_SRAM_STATE_RESET;
  208. /* Release Lock */
  209. __HAL_UNLOCK(hsram);
  210. return HAL_OK;
  211. }
  212. /**
  213. * @brief SRAM MSP Init.
  214. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  215. * the configuration information for SRAM module.
  216. * @retval None
  217. */
  218. __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
  219. {
  220. /* Prevent unused argument(s) compilation warning */
  221. UNUSED(hsram);
  222. /* NOTE : This function Should not be modified, when the callback is needed,
  223. the HAL_SRAM_MspInit could be implemented in the user file
  224. */
  225. }
  226. /**
  227. * @brief SRAM MSP DeInit.
  228. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  229. * the configuration information for SRAM module.
  230. * @retval None
  231. */
  232. __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
  233. {
  234. /* Prevent unused argument(s) compilation warning */
  235. UNUSED(hsram);
  236. /* NOTE : This function Should not be modified, when the callback is needed,
  237. the HAL_SRAM_MspDeInit could be implemented in the user file
  238. */
  239. }
  240. /**
  241. * @brief DMA transfer complete callback.
  242. * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
  243. * the configuration information for SRAM module.
  244. * @retval None
  245. */
  246. __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
  247. {
  248. /* Prevent unused argument(s) compilation warning */
  249. UNUSED(hdma);
  250. /* NOTE : This function Should not be modified, when the callback is needed,
  251. the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
  252. */
  253. }
  254. /**
  255. * @brief DMA transfer complete error callback.
  256. * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
  257. * the configuration information for SRAM module.
  258. * @retval None
  259. */
  260. __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
  261. {
  262. /* Prevent unused argument(s) compilation warning */
  263. UNUSED(hdma);
  264. /* NOTE : This function Should not be modified, when the callback is needed,
  265. the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
  266. */
  267. }
  268. /**
  269. * @}
  270. */
  271. /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
  272. * @brief Input Output and memory control functions
  273. *
  274. @verbatim
  275. ==============================================================================
  276. ##### SRAM Input and Output functions #####
  277. ==============================================================================
  278. [..]
  279. This section provides functions allowing to use and control the SRAM memory
  280. @endverbatim
  281. * @{
  282. */
  283. /**
  284. * @brief Reads 8-bit buffer from SRAM memory.
  285. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  286. * the configuration information for SRAM module.
  287. * @param pAddress Pointer to read start address
  288. * @param pDstBuffer Pointer to destination buffer
  289. * @param BufferSize Size of the buffer to read from memory
  290. * @retval HAL status
  291. */
  292. HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
  293. uint32_t BufferSize)
  294. {
  295. uint32_t size;
  296. __IO uint8_t *psramaddress = (uint8_t *)pAddress;
  297. uint8_t *pdestbuff = pDstBuffer;
  298. HAL_SRAM_StateTypeDef state = hsram->State;
  299. /* Check the SRAM controller state */
  300. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  301. {
  302. /* Process Locked */
  303. __HAL_LOCK(hsram);
  304. /* Update the SRAM controller state */
  305. hsram->State = HAL_SRAM_STATE_BUSY;
  306. /* Read data from memory */
  307. for (size = BufferSize; size != 0U; size--)
  308. {
  309. *pdestbuff = *psramaddress;
  310. pdestbuff++;
  311. psramaddress++;
  312. }
  313. /* Update the SRAM controller state */
  314. hsram->State = state;
  315. /* Process unlocked */
  316. __HAL_UNLOCK(hsram);
  317. }
  318. else
  319. {
  320. return HAL_ERROR;
  321. }
  322. return HAL_OK;
  323. }
  324. /**
  325. * @brief Writes 8-bit buffer to SRAM memory.
  326. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  327. * the configuration information for SRAM module.
  328. * @param pAddress Pointer to write start address
  329. * @param pSrcBuffer Pointer to source buffer to write
  330. * @param BufferSize Size of the buffer to write to memory
  331. * @retval HAL status
  332. */
  333. HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
  334. uint32_t BufferSize)
  335. {
  336. uint32_t size;
  337. __IO uint8_t *psramaddress = (uint8_t *)pAddress;
  338. uint8_t *psrcbuff = pSrcBuffer;
  339. /* Check the SRAM controller state */
  340. if (hsram->State == HAL_SRAM_STATE_READY)
  341. {
  342. /* Process Locked */
  343. __HAL_LOCK(hsram);
  344. /* Update the SRAM controller state */
  345. hsram->State = HAL_SRAM_STATE_BUSY;
  346. /* Write data to memory */
  347. for (size = BufferSize; size != 0U; size--)
  348. {
  349. *psramaddress = *psrcbuff;
  350. psrcbuff++;
  351. psramaddress++;
  352. }
  353. /* Update the SRAM controller state */
  354. hsram->State = HAL_SRAM_STATE_READY;
  355. /* Process unlocked */
  356. __HAL_UNLOCK(hsram);
  357. }
  358. else
  359. {
  360. return HAL_ERROR;
  361. }
  362. return HAL_OK;
  363. }
  364. /**
  365. * @brief Reads 16-bit buffer from SRAM memory.
  366. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  367. * the configuration information for SRAM module.
  368. * @param pAddress Pointer to read start address
  369. * @param pDstBuffer Pointer to destination buffer
  370. * @param BufferSize Size of the buffer to read from memory
  371. * @retval HAL status
  372. */
  373. HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
  374. uint32_t BufferSize)
  375. {
  376. uint32_t size;
  377. __IO uint32_t *psramaddress = pAddress;
  378. uint16_t *pdestbuff = pDstBuffer;
  379. uint8_t limit;
  380. HAL_SRAM_StateTypeDef state = hsram->State;
  381. /* Check the SRAM controller state */
  382. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  383. {
  384. /* Process Locked */
  385. __HAL_LOCK(hsram);
  386. /* Update the SRAM controller state */
  387. hsram->State = HAL_SRAM_STATE_BUSY;
  388. /* Check if the size is a 32-bits multiple */
  389. limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
  390. /* Read data from memory */
  391. for (size = BufferSize; size != limit; size -= 2U)
  392. {
  393. *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
  394. pdestbuff++;
  395. *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
  396. pdestbuff++;
  397. psramaddress++;
  398. }
  399. /* Read last 16-bits if size is not 32-bits multiple */
  400. if (limit != 0U)
  401. {
  402. *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
  403. }
  404. /* Update the SRAM controller state */
  405. hsram->State = state;
  406. /* Process unlocked */
  407. __HAL_UNLOCK(hsram);
  408. }
  409. else
  410. {
  411. return HAL_ERROR;
  412. }
  413. return HAL_OK;
  414. }
  415. /**
  416. * @brief Writes 16-bit buffer to SRAM memory.
  417. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  418. * the configuration information for SRAM module.
  419. * @param pAddress Pointer to write start address
  420. * @param pSrcBuffer Pointer to source buffer to write
  421. * @param BufferSize Size of the buffer to write to memory
  422. * @retval HAL status
  423. */
  424. HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
  425. uint32_t BufferSize)
  426. {
  427. uint32_t size;
  428. __IO uint32_t *psramaddress = pAddress;
  429. uint16_t *psrcbuff = pSrcBuffer;
  430. uint8_t limit;
  431. /* Check the SRAM controller state */
  432. if (hsram->State == HAL_SRAM_STATE_READY)
  433. {
  434. /* Process Locked */
  435. __HAL_LOCK(hsram);
  436. /* Update the SRAM controller state */
  437. hsram->State = HAL_SRAM_STATE_BUSY;
  438. /* Check if the size is a 32-bits multiple */
  439. limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
  440. /* Write data to memory */
  441. for (size = BufferSize; size != limit; size -= 2U)
  442. {
  443. *psramaddress = (uint32_t)(*psrcbuff);
  444. psrcbuff++;
  445. *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
  446. psrcbuff++;
  447. psramaddress++;
  448. }
  449. /* Write last 16-bits if size is not 32-bits multiple */
  450. if (limit != 0U)
  451. {
  452. *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
  453. }
  454. /* Update the SRAM controller state */
  455. hsram->State = HAL_SRAM_STATE_READY;
  456. /* Process unlocked */
  457. __HAL_UNLOCK(hsram);
  458. }
  459. else
  460. {
  461. return HAL_ERROR;
  462. }
  463. return HAL_OK;
  464. }
  465. /**
  466. * @brief Reads 32-bit buffer from SRAM memory.
  467. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  468. * the configuration information for SRAM module.
  469. * @param pAddress Pointer to read start address
  470. * @param pDstBuffer Pointer to destination buffer
  471. * @param BufferSize Size of the buffer to read from memory
  472. * @retval HAL status
  473. */
  474. HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
  475. uint32_t BufferSize)
  476. {
  477. uint32_t size;
  478. __IO uint32_t *psramaddress = pAddress;
  479. uint32_t *pdestbuff = pDstBuffer;
  480. HAL_SRAM_StateTypeDef state = hsram->State;
  481. /* Check the SRAM controller state */
  482. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  483. {
  484. /* Process Locked */
  485. __HAL_LOCK(hsram);
  486. /* Update the SRAM controller state */
  487. hsram->State = HAL_SRAM_STATE_BUSY;
  488. /* Read data from memory */
  489. for (size = BufferSize; size != 0U; size--)
  490. {
  491. *pdestbuff = *psramaddress;
  492. pdestbuff++;
  493. psramaddress++;
  494. }
  495. /* Update the SRAM controller state */
  496. hsram->State = state;
  497. /* Process unlocked */
  498. __HAL_UNLOCK(hsram);
  499. }
  500. else
  501. {
  502. return HAL_ERROR;
  503. }
  504. return HAL_OK;
  505. }
  506. /**
  507. * @brief Writes 32-bit buffer to SRAM memory.
  508. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  509. * the configuration information for SRAM module.
  510. * @param pAddress Pointer to write start address
  511. * @param pSrcBuffer Pointer to source buffer to write
  512. * @param BufferSize Size of the buffer to write to memory
  513. * @retval HAL status
  514. */
  515. HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
  516. uint32_t BufferSize)
  517. {
  518. uint32_t size;
  519. __IO uint32_t *psramaddress = pAddress;
  520. uint32_t *psrcbuff = pSrcBuffer;
  521. /* Check the SRAM controller state */
  522. if (hsram->State == HAL_SRAM_STATE_READY)
  523. {
  524. /* Process Locked */
  525. __HAL_LOCK(hsram);
  526. /* Update the SRAM controller state */
  527. hsram->State = HAL_SRAM_STATE_BUSY;
  528. /* Write data to memory */
  529. for (size = BufferSize; size != 0U; size--)
  530. {
  531. *psramaddress = *psrcbuff;
  532. psrcbuff++;
  533. psramaddress++;
  534. }
  535. /* Update the SRAM controller state */
  536. hsram->State = HAL_SRAM_STATE_READY;
  537. /* Process unlocked */
  538. __HAL_UNLOCK(hsram);
  539. }
  540. else
  541. {
  542. return HAL_ERROR;
  543. }
  544. return HAL_OK;
  545. }
  546. /**
  547. * @brief Reads a Words data from the SRAM memory using DMA transfer.
  548. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  549. * the configuration information for SRAM module.
  550. * @param pAddress Pointer to read start address
  551. * @param pDstBuffer Pointer to destination buffer
  552. * @param BufferSize Size of the buffer to read from memory
  553. * @retval HAL status
  554. */
  555. HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
  556. uint32_t BufferSize)
  557. {
  558. HAL_StatusTypeDef status;
  559. HAL_SRAM_StateTypeDef state = hsram->State;
  560. /* Check the SRAM controller state */
  561. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  562. {
  563. /* Process Locked */
  564. __HAL_LOCK(hsram);
  565. /* Update the SRAM controller state */
  566. hsram->State = HAL_SRAM_STATE_BUSY;
  567. /* Configure DMA user callbacks */
  568. if (state == HAL_SRAM_STATE_READY)
  569. {
  570. hsram->hdma->XferCpltCallback = SRAM_DMACplt;
  571. }
  572. else
  573. {
  574. hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
  575. }
  576. hsram->hdma->XferErrorCallback = SRAM_DMAError;
  577. /* Enable the DMA Stream */
  578. status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
  579. /* Process unlocked */
  580. __HAL_UNLOCK(hsram);
  581. }
  582. else
  583. {
  584. status = HAL_ERROR;
  585. }
  586. return status;
  587. }
  588. /**
  589. * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
  590. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  591. * the configuration information for SRAM module.
  592. * @param pAddress Pointer to write start address
  593. * @param pSrcBuffer Pointer to source buffer to write
  594. * @param BufferSize Size of the buffer to write to memory
  595. * @retval HAL status
  596. */
  597. HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
  598. uint32_t BufferSize)
  599. {
  600. HAL_StatusTypeDef status;
  601. /* Check the SRAM controller state */
  602. if (hsram->State == HAL_SRAM_STATE_READY)
  603. {
  604. /* Process Locked */
  605. __HAL_LOCK(hsram);
  606. /* Update the SRAM controller state */
  607. hsram->State = HAL_SRAM_STATE_BUSY;
  608. /* Configure DMA user callbacks */
  609. hsram->hdma->XferCpltCallback = SRAM_DMACplt;
  610. hsram->hdma->XferErrorCallback = SRAM_DMAError;
  611. /* Enable the DMA Stream */
  612. status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
  613. /* Process unlocked */
  614. __HAL_UNLOCK(hsram);
  615. }
  616. else
  617. {
  618. status = HAL_ERROR;
  619. }
  620. return status;
  621. }
  622. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  623. /**
  624. * @brief Register a User SRAM Callback
  625. * To be used to override the weak predefined callback
  626. * @param hsram : SRAM handle
  627. * @param CallbackId : ID of the callback to be registered
  628. * This parameter can be one of the following values:
  629. * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
  630. * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
  631. * @param pCallback : pointer to the Callback function
  632. * @retval status
  633. */
  634. HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
  635. pSRAM_CallbackTypeDef pCallback)
  636. {
  637. HAL_StatusTypeDef status = HAL_OK;
  638. HAL_SRAM_StateTypeDef state;
  639. if (pCallback == NULL)
  640. {
  641. return HAL_ERROR;
  642. }
  643. state = hsram->State;
  644. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
  645. {
  646. switch (CallbackId)
  647. {
  648. case HAL_SRAM_MSP_INIT_CB_ID :
  649. hsram->MspInitCallback = pCallback;
  650. break;
  651. case HAL_SRAM_MSP_DEINIT_CB_ID :
  652. hsram->MspDeInitCallback = pCallback;
  653. break;
  654. default :
  655. /* update return status */
  656. status = HAL_ERROR;
  657. break;
  658. }
  659. }
  660. else
  661. {
  662. /* update return status */
  663. status = HAL_ERROR;
  664. }
  665. return status;
  666. }
  667. /**
  668. * @brief Unregister a User SRAM Callback
  669. * SRAM Callback is redirected to the weak predefined callback
  670. * @param hsram : SRAM handle
  671. * @param CallbackId : ID of the callback to be unregistered
  672. * This parameter can be one of the following values:
  673. * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
  674. * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
  675. * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
  676. * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
  677. * @retval status
  678. */
  679. HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
  680. {
  681. HAL_StatusTypeDef status = HAL_OK;
  682. HAL_SRAM_StateTypeDef state;
  683. state = hsram->State;
  684. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  685. {
  686. switch (CallbackId)
  687. {
  688. case HAL_SRAM_MSP_INIT_CB_ID :
  689. hsram->MspInitCallback = HAL_SRAM_MspInit;
  690. break;
  691. case HAL_SRAM_MSP_DEINIT_CB_ID :
  692. hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
  693. break;
  694. case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
  695. hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
  696. break;
  697. case HAL_SRAM_DMA_XFER_ERR_CB_ID :
  698. hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
  699. break;
  700. default :
  701. /* update return status */
  702. status = HAL_ERROR;
  703. break;
  704. }
  705. }
  706. else if (state == HAL_SRAM_STATE_RESET)
  707. {
  708. switch (CallbackId)
  709. {
  710. case HAL_SRAM_MSP_INIT_CB_ID :
  711. hsram->MspInitCallback = HAL_SRAM_MspInit;
  712. break;
  713. case HAL_SRAM_MSP_DEINIT_CB_ID :
  714. hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
  715. break;
  716. default :
  717. /* update return status */
  718. status = HAL_ERROR;
  719. break;
  720. }
  721. }
  722. else
  723. {
  724. /* update return status */
  725. status = HAL_ERROR;
  726. }
  727. return status;
  728. }
  729. /**
  730. * @brief Register a User SRAM Callback for DMA transfers
  731. * To be used to override the weak predefined callback
  732. * @param hsram : SRAM handle
  733. * @param CallbackId : ID of the callback to be registered
  734. * This parameter can be one of the following values:
  735. * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
  736. * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
  737. * @param pCallback : pointer to the Callback function
  738. * @retval status
  739. */
  740. HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
  741. pSRAM_DmaCallbackTypeDef pCallback)
  742. {
  743. HAL_StatusTypeDef status = HAL_OK;
  744. HAL_SRAM_StateTypeDef state;
  745. if (pCallback == NULL)
  746. {
  747. return HAL_ERROR;
  748. }
  749. /* Process locked */
  750. __HAL_LOCK(hsram);
  751. state = hsram->State;
  752. if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
  753. {
  754. switch (CallbackId)
  755. {
  756. case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
  757. hsram->DmaXferCpltCallback = pCallback;
  758. break;
  759. case HAL_SRAM_DMA_XFER_ERR_CB_ID :
  760. hsram->DmaXferErrorCallback = pCallback;
  761. break;
  762. default :
  763. /* update return status */
  764. status = HAL_ERROR;
  765. break;
  766. }
  767. }
  768. else
  769. {
  770. /* update return status */
  771. status = HAL_ERROR;
  772. }
  773. /* Release Lock */
  774. __HAL_UNLOCK(hsram);
  775. return status;
  776. }
  777. #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
  778. /**
  779. * @}
  780. */
  781. /** @defgroup SRAM_Exported_Functions_Group3 Control functions
  782. * @brief Control functions
  783. *
  784. @verbatim
  785. ==============================================================================
  786. ##### SRAM Control functions #####
  787. ==============================================================================
  788. [..]
  789. This subsection provides a set of functions allowing to control dynamically
  790. the SRAM interface.
  791. @endverbatim
  792. * @{
  793. */
  794. /**
  795. * @brief Enables dynamically SRAM write operation.
  796. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  797. * the configuration information for SRAM module.
  798. * @retval HAL status
  799. */
  800. HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
  801. {
  802. /* Check the SRAM controller state */
  803. if (hsram->State == HAL_SRAM_STATE_PROTECTED)
  804. {
  805. /* Process Locked */
  806. __HAL_LOCK(hsram);
  807. /* Update the SRAM controller state */
  808. hsram->State = HAL_SRAM_STATE_BUSY;
  809. /* Enable write operation */
  810. (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
  811. /* Update the SRAM controller state */
  812. hsram->State = HAL_SRAM_STATE_READY;
  813. /* Process unlocked */
  814. __HAL_UNLOCK(hsram);
  815. }
  816. else
  817. {
  818. return HAL_ERROR;
  819. }
  820. return HAL_OK;
  821. }
  822. /**
  823. * @brief Disables dynamically SRAM write operation.
  824. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  825. * the configuration information for SRAM module.
  826. * @retval HAL status
  827. */
  828. HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
  829. {
  830. /* Check the SRAM controller state */
  831. if (hsram->State == HAL_SRAM_STATE_READY)
  832. {
  833. /* Process Locked */
  834. __HAL_LOCK(hsram);
  835. /* Update the SRAM controller state */
  836. hsram->State = HAL_SRAM_STATE_BUSY;
  837. /* Disable write operation */
  838. (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
  839. /* Update the SRAM controller state */
  840. hsram->State = HAL_SRAM_STATE_PROTECTED;
  841. /* Process unlocked */
  842. __HAL_UNLOCK(hsram);
  843. }
  844. else
  845. {
  846. return HAL_ERROR;
  847. }
  848. return HAL_OK;
  849. }
  850. /**
  851. * @}
  852. */
  853. /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
  854. * @brief Peripheral State functions
  855. *
  856. @verbatim
  857. ==============================================================================
  858. ##### SRAM State functions #####
  859. ==============================================================================
  860. [..]
  861. This subsection permits to get in run-time the status of the SRAM controller
  862. and the data flow.
  863. @endverbatim
  864. * @{
  865. */
  866. /**
  867. * @brief Returns the SRAM controller state
  868. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
  869. * the configuration information for SRAM module.
  870. * @retval HAL state
  871. */
  872. HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
  873. {
  874. return hsram->State;
  875. }
  876. /**
  877. * @}
  878. */
  879. /**
  880. * @}
  881. */
  882. /** @addtogroup SRAM_Private_Functions SRAM Private Functions
  883. * @{
  884. */
  885. /**
  886. * @brief DMA SRAM process complete callback.
  887. * @param hdma : DMA handle
  888. * @retval None
  889. */
  890. static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
  891. {
  892. SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
  893. /* Disable the DMA channel */
  894. __HAL_DMA_DISABLE(hdma);
  895. /* Update the SRAM controller state */
  896. hsram->State = HAL_SRAM_STATE_READY;
  897. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  898. hsram->DmaXferCpltCallback(hdma);
  899. #else
  900. HAL_SRAM_DMA_XferCpltCallback(hdma);
  901. #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
  902. }
  903. /**
  904. * @brief DMA SRAM process complete callback.
  905. * @param hdma : DMA handle
  906. * @retval None
  907. */
  908. static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
  909. {
  910. SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
  911. /* Disable the DMA channel */
  912. __HAL_DMA_DISABLE(hdma);
  913. /* Update the SRAM controller state */
  914. hsram->State = HAL_SRAM_STATE_PROTECTED;
  915. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  916. hsram->DmaXferCpltCallback(hdma);
  917. #else
  918. HAL_SRAM_DMA_XferCpltCallback(hdma);
  919. #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
  920. }
  921. /**
  922. * @brief DMA SRAM error callback.
  923. * @param hdma : DMA handle
  924. * @retval None
  925. */
  926. static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
  927. {
  928. SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
  929. /* Disable the DMA channel */
  930. __HAL_DMA_DISABLE(hdma);
  931. /* Update the SRAM controller state */
  932. hsram->State = HAL_SRAM_STATE_ERROR;
  933. #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
  934. hsram->DmaXferErrorCallback(hdma);
  935. #else
  936. HAL_SRAM_DMA_XferErrorCallback(hdma);
  937. #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
  938. }
  939. /**
  940. * @}
  941. */
  942. /**
  943. * @}
  944. */
  945. #endif /* HAL_SRAM_MODULE_ENABLED */
  946. /**
  947. * @}
  948. */
  949. #endif /* FSMC_BANK1 */