stm32f4xx_dma.h 28 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_dma.h
  4. * @author MCD Application Team
  5. * @version V1.5.0
  6. * @date 06-March-2015
  7. * @brief This file contains all the functions prototypes for the DMA firmware
  8. * library.
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
  13. *
  14. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  15. * You may not use this file except in compliance with the License.
  16. * You may obtain a copy of the License at:
  17. *
  18. * http://www.st.com/software_license_agreement_liberty_v2
  19. *
  20. * Unless required by applicable law or agreed to in writing, software
  21. * distributed under the License is distributed on an "AS IS" BASIS,
  22. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  23. * See the License for the specific language governing permissions and
  24. * limitations under the License.
  25. *
  26. ******************************************************************************
  27. */
  28. /* Define to prevent recursive inclusion -------------------------------------*/
  29. #ifndef __STM32F4xx_DMA_H
  30. #define __STM32F4xx_DMA_H
  31. #ifdef __cplusplus
  32. extern "C" {
  33. #endif
  34. /* Includes ------------------------------------------------------------------*/
  35. #include "stm32f4xx.h"
  36. /** @addtogroup STM32F4xx_StdPeriph_Driver
  37. * @{
  38. */
  39. /** @addtogroup DMA
  40. * @{
  41. */
  42. /* Exported types ------------------------------------------------------------*/
  43. /**
  44. * @brief DMA Init structure definition
  45. */
  46. typedef struct
  47. {
  48. uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
  49. This parameter can be a value of @ref DMA_channel */
  50. uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
  51. uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
  52. This memory is the default memory used when double buffer mode is
  53. not enabled. */
  54. uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
  55. from memory to memory or from peripheral to memory.
  56. This parameter can be a value of @ref DMA_data_transfer_direction */
  57. uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
  58. The data unit is equal to the configuration set in DMA_PeripheralDataSize
  59. or DMA_MemoryDataSize members depending in the transfer direction. */
  60. uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
  61. This parameter can be a value of @ref DMA_peripheral_incremented_mode */
  62. uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
  63. This parameter can be a value of @ref DMA_memory_incremented_mode */
  64. uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
  65. This parameter can be a value of @ref DMA_peripheral_data_size */
  66. uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
  67. This parameter can be a value of @ref DMA_memory_data_size */
  68. uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
  69. This parameter can be a value of @ref DMA_circular_normal_mode
  70. @note The circular buffer mode cannot be used if the memory-to-memory
  71. data transfer is configured on the selected Stream */
  72. uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
  73. This parameter can be a value of @ref DMA_priority_level */
  74. uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
  75. This parameter can be a value of @ref DMA_fifo_direct_mode
  76. @note The Direct mode (FIFO mode disabled) cannot be used if the
  77. memory-to-memory data transfer is configured on the selected Stream */
  78. uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
  79. This parameter can be a value of @ref DMA_fifo_threshold_level */
  80. uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
  81. It specifies the amount of data to be transferred in a single non interruptable
  82. transaction. This parameter can be a value of @ref DMA_memory_burst
  83. @note The burst mode is possible only if the address Increment mode is enabled. */
  84. uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
  85. It specifies the amount of data to be transferred in a single non interruptable
  86. transaction. This parameter can be a value of @ref DMA_peripheral_burst
  87. @note The burst mode is possible only if the address Increment mode is enabled. */
  88. }DMA_InitTypeDef;
  89. /* Exported constants --------------------------------------------------------*/
  90. /** @defgroup DMA_Exported_Constants
  91. * @{
  92. */
  93. #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
  94. ((PERIPH) == DMA1_Stream1) || \
  95. ((PERIPH) == DMA1_Stream2) || \
  96. ((PERIPH) == DMA1_Stream3) || \
  97. ((PERIPH) == DMA1_Stream4) || \
  98. ((PERIPH) == DMA1_Stream5) || \
  99. ((PERIPH) == DMA1_Stream6) || \
  100. ((PERIPH) == DMA1_Stream7) || \
  101. ((PERIPH) == DMA2_Stream0) || \
  102. ((PERIPH) == DMA2_Stream1) || \
  103. ((PERIPH) == DMA2_Stream2) || \
  104. ((PERIPH) == DMA2_Stream3) || \
  105. ((PERIPH) == DMA2_Stream4) || \
  106. ((PERIPH) == DMA2_Stream5) || \
  107. ((PERIPH) == DMA2_Stream6) || \
  108. ((PERIPH) == DMA2_Stream7))
  109. #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
  110. ((CONTROLLER) == DMA2))
  111. /** @defgroup DMA_channel
  112. * @{
  113. */
  114. #define DMA_Channel_0 ((uint32_t)0x00000000)
  115. #define DMA_Channel_1 ((uint32_t)0x02000000)
  116. #define DMA_Channel_2 ((uint32_t)0x04000000)
  117. #define DMA_Channel_3 ((uint32_t)0x06000000)
  118. #define DMA_Channel_4 ((uint32_t)0x08000000)
  119. #define DMA_Channel_5 ((uint32_t)0x0A000000)
  120. #define DMA_Channel_6 ((uint32_t)0x0C000000)
  121. #define DMA_Channel_7 ((uint32_t)0x0E000000)
  122. #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
  123. ((CHANNEL) == DMA_Channel_1) || \
  124. ((CHANNEL) == DMA_Channel_2) || \
  125. ((CHANNEL) == DMA_Channel_3) || \
  126. ((CHANNEL) == DMA_Channel_4) || \
  127. ((CHANNEL) == DMA_Channel_5) || \
  128. ((CHANNEL) == DMA_Channel_6) || \
  129. ((CHANNEL) == DMA_Channel_7))
  130. /**
  131. * @}
  132. */
  133. /** @defgroup DMA_data_transfer_direction
  134. * @{
  135. */
  136. #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
  137. #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
  138. #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
  139. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
  140. ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
  141. ((DIRECTION) == DMA_DIR_MemoryToMemory))
  142. /**
  143. * @}
  144. */
  145. /** @defgroup DMA_data_buffer_size
  146. * @{
  147. */
  148. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
  149. /**
  150. * @}
  151. */
  152. /** @defgroup DMA_peripheral_incremented_mode
  153. * @{
  154. */
  155. #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
  156. #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
  157. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
  158. ((STATE) == DMA_PeripheralInc_Disable))
  159. /**
  160. * @}
  161. */
  162. /** @defgroup DMA_memory_incremented_mode
  163. * @{
  164. */
  165. #define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
  166. #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
  167. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
  168. ((STATE) == DMA_MemoryInc_Disable))
  169. /**
  170. * @}
  171. */
  172. /** @defgroup DMA_peripheral_data_size
  173. * @{
  174. */
  175. #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
  176. #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
  177. #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
  178. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
  179. ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
  180. ((SIZE) == DMA_PeripheralDataSize_Word))
  181. /**
  182. * @}
  183. */
  184. /** @defgroup DMA_memory_data_size
  185. * @{
  186. */
  187. #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
  188. #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
  189. #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
  190. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
  191. ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
  192. ((SIZE) == DMA_MemoryDataSize_Word ))
  193. /**
  194. * @}
  195. */
  196. /** @defgroup DMA_circular_normal_mode
  197. * @{
  198. */
  199. #define DMA_Mode_Normal ((uint32_t)0x00000000)
  200. #define DMA_Mode_Circular ((uint32_t)0x00000100)
  201. #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
  202. ((MODE) == DMA_Mode_Circular))
  203. /**
  204. * @}
  205. */
  206. /** @defgroup DMA_priority_level
  207. * @{
  208. */
  209. #define DMA_Priority_Low ((uint32_t)0x00000000)
  210. #define DMA_Priority_Medium ((uint32_t)0x00010000)
  211. #define DMA_Priority_High ((uint32_t)0x00020000)
  212. #define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
  213. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
  214. ((PRIORITY) == DMA_Priority_Medium) || \
  215. ((PRIORITY) == DMA_Priority_High) || \
  216. ((PRIORITY) == DMA_Priority_VeryHigh))
  217. /**
  218. * @}
  219. */
  220. /** @defgroup DMA_fifo_direct_mode
  221. * @{
  222. */
  223. #define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
  224. #define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
  225. #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
  226. ((STATE) == DMA_FIFOMode_Enable))
  227. /**
  228. * @}
  229. */
  230. /** @defgroup DMA_fifo_threshold_level
  231. * @{
  232. */
  233. #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
  234. #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
  235. #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
  236. #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
  237. #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
  238. ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
  239. ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
  240. ((THRESHOLD) == DMA_FIFOThreshold_Full))
  241. /**
  242. * @}
  243. */
  244. /** @defgroup DMA_memory_burst
  245. * @{
  246. */
  247. #define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
  248. #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
  249. #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
  250. #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
  251. #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
  252. ((BURST) == DMA_MemoryBurst_INC4) || \
  253. ((BURST) == DMA_MemoryBurst_INC8) || \
  254. ((BURST) == DMA_MemoryBurst_INC16))
  255. /**
  256. * @}
  257. */
  258. /** @defgroup DMA_peripheral_burst
  259. * @{
  260. */
  261. #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
  262. #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
  263. #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
  264. #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
  265. #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
  266. ((BURST) == DMA_PeripheralBurst_INC4) || \
  267. ((BURST) == DMA_PeripheralBurst_INC8) || \
  268. ((BURST) == DMA_PeripheralBurst_INC16))
  269. /**
  270. * @}
  271. */
  272. /** @defgroup DMA_fifo_status_level
  273. * @{
  274. */
  275. #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
  276. #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
  277. #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
  278. #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
  279. #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
  280. #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
  281. #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
  282. ((STATUS) == DMA_FIFOStatus_HalfFull) || \
  283. ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
  284. ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
  285. ((STATUS) == DMA_FIFOStatus_Full) || \
  286. ((STATUS) == DMA_FIFOStatus_Empty))
  287. /**
  288. * @}
  289. */
  290. /** @defgroup DMA_flags_definition
  291. * @{
  292. */
  293. #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
  294. #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
  295. #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
  296. #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
  297. #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
  298. #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
  299. #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
  300. #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
  301. #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
  302. #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
  303. #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
  304. #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
  305. #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
  306. #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
  307. #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
  308. #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
  309. #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
  310. #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
  311. #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
  312. #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
  313. #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
  314. #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
  315. #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
  316. #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
  317. #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
  318. #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
  319. #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
  320. #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
  321. #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
  322. #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
  323. #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
  324. #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
  325. #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
  326. #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
  327. #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
  328. #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
  329. #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
  330. #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
  331. #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
  332. #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
  333. #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
  334. (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
  335. #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
  336. ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
  337. ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
  338. ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
  339. ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
  340. ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
  341. ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
  342. ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
  343. ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
  344. ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
  345. ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
  346. ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
  347. ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
  348. ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
  349. ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
  350. ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
  351. ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
  352. ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
  353. ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
  354. ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
  355. /**
  356. * @}
  357. */
  358. /** @defgroup DMA_interrupt_enable_definitions
  359. * @{
  360. */
  361. #define DMA_IT_TC ((uint32_t)0x00000010)
  362. #define DMA_IT_HT ((uint32_t)0x00000008)
  363. #define DMA_IT_TE ((uint32_t)0x00000004)
  364. #define DMA_IT_DME ((uint32_t)0x00000002)
  365. #define DMA_IT_FE ((uint32_t)0x00000080)
  366. #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
  367. /**
  368. * @}
  369. */
  370. /** @defgroup DMA_interrupts_definitions
  371. * @{
  372. */
  373. #define DMA_IT_FEIF0 ((uint32_t)0x90000001)
  374. #define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
  375. #define DMA_IT_TEIF0 ((uint32_t)0x10002008)
  376. #define DMA_IT_HTIF0 ((uint32_t)0x10004010)
  377. #define DMA_IT_TCIF0 ((uint32_t)0x10008020)
  378. #define DMA_IT_FEIF1 ((uint32_t)0x90000040)
  379. #define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
  380. #define DMA_IT_TEIF1 ((uint32_t)0x10002200)
  381. #define DMA_IT_HTIF1 ((uint32_t)0x10004400)
  382. #define DMA_IT_TCIF1 ((uint32_t)0x10008800)
  383. #define DMA_IT_FEIF2 ((uint32_t)0x90010000)
  384. #define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
  385. #define DMA_IT_TEIF2 ((uint32_t)0x10082000)
  386. #define DMA_IT_HTIF2 ((uint32_t)0x10104000)
  387. #define DMA_IT_TCIF2 ((uint32_t)0x10208000)
  388. #define DMA_IT_FEIF3 ((uint32_t)0x90400000)
  389. #define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
  390. #define DMA_IT_TEIF3 ((uint32_t)0x12002000)
  391. #define DMA_IT_HTIF3 ((uint32_t)0x14004000)
  392. #define DMA_IT_TCIF3 ((uint32_t)0x18008000)
  393. #define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
  394. #define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
  395. #define DMA_IT_TEIF4 ((uint32_t)0x20002008)
  396. #define DMA_IT_HTIF4 ((uint32_t)0x20004010)
  397. #define DMA_IT_TCIF4 ((uint32_t)0x20008020)
  398. #define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
  399. #define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
  400. #define DMA_IT_TEIF5 ((uint32_t)0x20002200)
  401. #define DMA_IT_HTIF5 ((uint32_t)0x20004400)
  402. #define DMA_IT_TCIF5 ((uint32_t)0x20008800)
  403. #define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
  404. #define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
  405. #define DMA_IT_TEIF6 ((uint32_t)0x20082000)
  406. #define DMA_IT_HTIF6 ((uint32_t)0x20104000)
  407. #define DMA_IT_TCIF6 ((uint32_t)0x20208000)
  408. #define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
  409. #define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
  410. #define DMA_IT_TEIF7 ((uint32_t)0x22002000)
  411. #define DMA_IT_HTIF7 ((uint32_t)0x24004000)
  412. #define DMA_IT_TCIF7 ((uint32_t)0x28008000)
  413. #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
  414. (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
  415. (((IT) & 0x40820082) == 0x00))
  416. #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
  417. ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
  418. ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
  419. ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
  420. ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
  421. ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
  422. ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
  423. ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
  424. ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
  425. ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
  426. ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
  427. ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
  428. ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
  429. ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
  430. ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
  431. ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
  432. ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
  433. ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
  434. ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
  435. ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
  436. /**
  437. * @}
  438. */
  439. /** @defgroup DMA_peripheral_increment_offset
  440. * @{
  441. */
  442. #define DMA_PINCOS_Psize ((uint32_t)0x00000000)
  443. #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
  444. #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
  445. ((SIZE) == DMA_PINCOS_WordAligned))
  446. /**
  447. * @}
  448. */
  449. /** @defgroup DMA_flow_controller_definitions
  450. * @{
  451. */
  452. #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
  453. #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
  454. #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
  455. ((CTRL) == DMA_FlowCtrl_Peripheral))
  456. /**
  457. * @}
  458. */
  459. /** @defgroup DMA_memory_targets_definitions
  460. * @{
  461. */
  462. #define DMA_Memory_0 ((uint32_t)0x00000000)
  463. #define DMA_Memory_1 ((uint32_t)0x00080000)
  464. #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
  465. /**
  466. * @}
  467. */
  468. /**
  469. * @}
  470. */
  471. /* Exported macro ------------------------------------------------------------*/
  472. /* Exported functions --------------------------------------------------------*/
  473. /* Function used to set the DMA configuration to the default reset state *****/
  474. void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
  475. /* Initialization and Configuration functions *********************************/
  476. void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
  477. void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
  478. void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
  479. /* Optional Configuration functions *******************************************/
  480. void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
  481. void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
  482. /* Data Counter functions *****************************************************/
  483. void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
  484. uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
  485. /* Double Buffer mode functions ***********************************************/
  486. void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
  487. uint32_t DMA_CurrentMemory);
  488. void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
  489. void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
  490. uint32_t DMA_MemoryTarget);
  491. uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
  492. /* Interrupts and flags management functions **********************************/
  493. FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
  494. uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
  495. FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
  496. void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
  497. void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
  498. ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
  499. void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
  500. #ifdef __cplusplus
  501. }
  502. #endif
  503. #endif /*__STM32F4xx_DMA_H */
  504. /**
  505. * @}
  506. */
  507. /**
  508. * @}
  509. */
  510. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/