arm_cmplx_mag_q15.c 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153
  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_cmplx_mag_q15.c
  9. *
  10. * Description: Q15 complex magnitude.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * ---------------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupCmplxMath
  43. */
  44. /**
  45. * @addtogroup cmplx_mag
  46. * @{
  47. */
  48. /**
  49. * @brief Q15 complex magnitude
  50. * @param *pSrc points to the complex input vector
  51. * @param *pDst points to the real output vector
  52. * @param numSamples number of complex samples in the input vector
  53. * @return none.
  54. *
  55. * <b>Scaling and Overflow Behavior:</b>
  56. * \par
  57. * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
  58. */
  59. void arm_cmplx_mag_q15(
  60. q15_t * pSrc,
  61. q15_t * pDst,
  62. uint32_t numSamples)
  63. {
  64. q31_t acc0, acc1; /* Accumulators */
  65. #ifndef ARM_MATH_CM0_FAMILY
  66. /* Run the below code for Cortex-M4 and Cortex-M3 */
  67. uint32_t blkCnt; /* loop counter */
  68. q31_t in1, in2, in3, in4;
  69. q31_t acc2, acc3;
  70. /*loop Unrolling */
  71. blkCnt = numSamples >> 2u;
  72. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  73. ** a second loop below computes the remaining 1 to 3 samples. */
  74. while(blkCnt > 0u)
  75. {
  76. /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
  77. in1 = *__SIMD32(pSrc)++;
  78. in2 = *__SIMD32(pSrc)++;
  79. in3 = *__SIMD32(pSrc)++;
  80. in4 = *__SIMD32(pSrc)++;
  81. acc0 = __SMUAD(in1, in1);
  82. acc1 = __SMUAD(in2, in2);
  83. acc2 = __SMUAD(in3, in3);
  84. acc3 = __SMUAD(in4, in4);
  85. /* store the result in 2.14 format in the destination buffer. */
  86. arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
  87. arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
  88. arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
  89. arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
  90. /* Decrement the loop counter */
  91. blkCnt--;
  92. }
  93. /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
  94. ** No loop unrolling is used. */
  95. blkCnt = numSamples % 0x4u;
  96. while(blkCnt > 0u)
  97. {
  98. /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
  99. in1 = *__SIMD32(pSrc)++;
  100. acc0 = __SMUAD(in1, in1);
  101. /* store the result in 2.14 format in the destination buffer. */
  102. arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
  103. /* Decrement the loop counter */
  104. blkCnt--;
  105. }
  106. #else
  107. /* Run the below code for Cortex-M0 */
  108. q15_t real, imag; /* Temporary variables to hold input values */
  109. while(numSamples > 0u)
  110. {
  111. /* out = sqrt(real * real + imag * imag) */
  112. real = *pSrc++;
  113. imag = *pSrc++;
  114. acc0 = (real * real);
  115. acc1 = (imag * imag);
  116. /* store the result in 2.14 format in the destination buffer. */
  117. arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
  118. /* Decrement the loop counter */
  119. numSamples--;
  120. }
  121. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  122. }
  123. /**
  124. * @} end of cmplx_mag group
  125. */