arm_sub_f32.c 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150
  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_sub_f32.c
  9. *
  10. * Description: Floating-point vector subtraction.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * ---------------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupMath
  43. */
  44. /**
  45. * @defgroup BasicSub Vector Subtraction
  46. *
  47. * Element-by-element subtraction of two vectors.
  48. *
  49. * <pre>
  50. * pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
  51. * </pre>
  52. *
  53. * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
  54. */
  55. /**
  56. * @addtogroup BasicSub
  57. * @{
  58. */
  59. /**
  60. * @brief Floating-point vector subtraction.
  61. * @param[in] *pSrcA points to the first input vector
  62. * @param[in] *pSrcB points to the second input vector
  63. * @param[out] *pDst points to the output vector
  64. * @param[in] blockSize number of samples in each vector
  65. * @return none.
  66. */
  67. void arm_sub_f32(
  68. float32_t * pSrcA,
  69. float32_t * pSrcB,
  70. float32_t * pDst,
  71. uint32_t blockSize)
  72. {
  73. uint32_t blkCnt; /* loop counter */
  74. #ifndef ARM_MATH_CM0_FAMILY
  75. /* Run the below code for Cortex-M4 and Cortex-M3 */
  76. float32_t inA1, inA2, inA3, inA4; /* temporary variables */
  77. float32_t inB1, inB2, inB3, inB4; /* temporary variables */
  78. /*loop Unrolling */
  79. blkCnt = blockSize >> 2u;
  80. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  81. ** a second loop below computes the remaining 1 to 3 samples. */
  82. while(blkCnt > 0u)
  83. {
  84. /* C = A - B */
  85. /* Subtract and then store the results in the destination buffer. */
  86. /* Read 4 input samples from sourceA and sourceB */
  87. inA1 = *pSrcA;
  88. inB1 = *pSrcB;
  89. inA2 = *(pSrcA + 1);
  90. inB2 = *(pSrcB + 1);
  91. inA3 = *(pSrcA + 2);
  92. inB3 = *(pSrcB + 2);
  93. inA4 = *(pSrcA + 3);
  94. inB4 = *(pSrcB + 3);
  95. /* dst = srcA - srcB */
  96. /* subtract and store the result */
  97. *pDst = inA1 - inB1;
  98. *(pDst + 1) = inA2 - inB2;
  99. *(pDst + 2) = inA3 - inB3;
  100. *(pDst + 3) = inA4 - inB4;
  101. /* Update pointers to process next sampels */
  102. pSrcA += 4u;
  103. pSrcB += 4u;
  104. pDst += 4u;
  105. /* Decrement the loop counter */
  106. blkCnt--;
  107. }
  108. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
  109. ** No loop unrolling is used. */
  110. blkCnt = blockSize % 0x4u;
  111. #else
  112. /* Run the below code for Cortex-M0 */
  113. /* Initialize blkCnt with number of samples */
  114. blkCnt = blockSize;
  115. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  116. while(blkCnt > 0u)
  117. {
  118. /* C = A - B */
  119. /* Subtract and then store the results in the destination buffer. */
  120. *pDst++ = (*pSrcA++) - (*pSrcB++);
  121. /* Decrement the loop counter */
  122. blkCnt--;
  123. }
  124. }
  125. /**
  126. * @} end of BasicSub group
  127. */