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- [platformio]
- src_dir = ./
- ; include_dir = User
- build_dir = Build
- [env:genericSTM32F407IGT6]
- platform = ststm32
- board = genericSTM32F407IGT6
- board_build.cmsis.custom_config_header = yes
- ; 表示使用项目目录下的链接文件
- board_build.ldscript = Project/GCC/STM32F417IG_FLASH.ld
- extra_scripts = Project/GCC/scripts.py
- monitor_speed = 9600
- build_flags =
- -IUser
- ; -IUser/bsp
- -IUser/bsp/can
- -IUser/bsp/eth
- -IUser/bsp/interface
- -IUser/bsp/iwdg
- -IUser/bsp/timer
- -IUser/bsp/uart
- -IUser/app
- -IUser/app/queue
- -IUser/app/led
- -IUser/app/modbus
- -IUser/app/dm9k
- -IUser/app/net
- -IUser/config/lwip
- -IUser/config/ucos
- -ILibraries/CMSIS/Include
- -ILibraries/CMSIS/Device/ST/STM32F4xx/Include
- -ILibraries/STM32F4xx_StdPeriph_Driver/inc
- -ILibraries/STM32F4x7_ETH_Driver/inc
- -IMiddleWare/uCOS_II/uC-CPU
- -IMiddleWare/uCOS_II/uC-CPU/ARM-Cortex-M4/GNU
- -IMiddleWare/uCOS_II/uC-LIB
- -IMiddleWare/uCOS_II/uCOS-BSP
- -IMiddleWare/uCOS_II/uCOS-II/Source
- -IMiddleWare/uCOS_II/uCOS-II/Ports/ARM-Cortex-M4/Generic/GNU
- -IMiddleWare/lwip-2.0.2/src/include
- -IMiddleWare/lwip-2.0.2/src/include/lwip
- -IMiddleWare/lwip-2.0.2/src/include/netif
- -IMiddleWare/lwip-2.0.2/src/include/posix
- -IMiddleWare/lwip-2.0.2/src/include/posix/sys
- -IMiddleWare/lwip-2.0.2/port/STM32F4xx
- -IMiddleWare/lwip-2.0.2/port/STM32F4xx/arch
- -IMiddleWare/lwip-2.0.2/port/STM32F4xx/UCOS_II
- ; 定义全局宏
- -D STM32F40_41xxx
- -D USE_STDPERIPH_DRIVER
- build_unflags =
- -DSTM32F407xx
- -DSTM32F4
- src_filter = +<User/>
- +<Project/GCC/>
- ; -<User/app/dm9k>
- +<Libraries/STM32F4xx_StdPeriph_Driver/src/>
- -<Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_qspi.c>
- -<Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmpi2c.c>
- -<Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c>
- -<Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cec.c>
- -<Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spdifrx.c>
- +<Libraries/STM32F4x7_ETH_Driver/src/>
- +<MiddleWare/lwip-2.0.2/src/api>
- +<MiddleWare/lwip-2.0.2/src/core>
- +<MiddleWare/lwip-2.0.2/src/core/ipv4>
- +<MiddleWare/lwip-2.0.2/src/core/snmp>
- +<MiddleWare/lwip-2.0.2/src/netif>
- +<MiddleWare/lwip-2.0.2/src/netif/ppp>
- +<MiddleWare/lwip-2.0.2/port/STM32F4xx/arch>
- +<MiddleWare/lwip-2.0.2/port/STM32F4xx/uCOS_II>
- +<MiddleWare/uCOS_II>
- -<MiddleWare/uCOS_II/uC-CPU/ARM-Cortex-M0>
- -<MiddleWare/uCOS_II/uC-CPU/ARM-Cortex-M3>
- -<MiddleWare/uCOS_II/uC-CPU/ARM-Cortex-M4/RealView>
- -<MiddleWare/uCOS_II/uC-CPU/ARM-Cortex-M4/IAR>
- -<MiddleWare/uCOS_II/uC-LIB/Ports/ARM-Cortex-M0>
- -<MiddleWare/uCOS_II/uC-LIB/Ports/ARM-Cortex-M3>
- -<MiddleWare/uCOS_II/uC-LIB/Ports/ARM-Cortex-M4/IAR>
- -<MiddleWare/uCOS_II/uC-LIB/Ports/ARM-Cortex-M4/RealView>
- -<MiddleWare/uCOS_II/uC-LIB/Ports/ARM-Cortex-M4/RealView>
- -<MiddleWare/uCOS_II/uCOS-II/Ports/ARM-Cortex-M0>
- -<MiddleWare/uCOS_II/uCOS-II/Ports/ARM-Cortex-M3>
- -<MiddleWare/uCOS_II/uCOS-II/Ports/ARM-Cortex-M4/Generic/IAR>
- -<MiddleWare/uCOS_II/uCOS-II/Ports/ARM-Cortex-M4/Generic/RealView>
- debug_tool = stlink
- upload_protocol = stlink
- ; upload_protocol = custom
- ; upload_command = st-flash --reset write $SOURCE 0x8000000
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