arm_cfft_q15.c 9.8 KB

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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 31. July 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_cfft_q15.c
  9. *
  10. * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. extern void arm_radix4_butterfly_q15(
  42. q15_t * pSrc,
  43. uint32_t fftLen,
  44. q15_t * pCoef,
  45. uint32_t twidCoefModifier);
  46. extern void arm_radix4_butterfly_inverse_q15(
  47. q15_t * pSrc,
  48. uint32_t fftLen,
  49. q15_t * pCoef,
  50. uint32_t twidCoefModifier);
  51. extern void arm_bitreversal_16(
  52. uint16_t * pSrc,
  53. const uint16_t bitRevLen,
  54. const uint16_t * pBitRevTable);
  55. void arm_cfft_radix4by2_q15(
  56. q15_t * pSrc,
  57. uint32_t fftLen,
  58. const q15_t * pCoef);
  59. void arm_cfft_radix4by2_inverse_q15(
  60. q15_t * pSrc,
  61. uint32_t fftLen,
  62. const q15_t * pCoef);
  63. /**
  64. * @ingroup groupTransforms
  65. */
  66. /**
  67. * @addtogroup ComplexFFT
  68. * @{
  69. */
  70. /**
  71. * @details
  72. * @brief Processing function for the floating-point complex FFT.
  73. * @param[in] *S points to an instance of the floating-point CFFT structure.
  74. * @param[in, out] *p1 points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
  75. * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
  76. * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
  77. * @return none.
  78. */
  79. void arm_cfft_q15(
  80. const arm_cfft_instance_q15 * S,
  81. q15_t * p1,
  82. uint8_t ifftFlag,
  83. uint8_t bitReverseFlag)
  84. {
  85. uint32_t L = S->fftLen;
  86. if(ifftFlag == 1u)
  87. {
  88. switch (L)
  89. {
  90. case 16:
  91. case 64:
  92. case 256:
  93. case 1024:
  94. case 4096:
  95. arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 );
  96. break;
  97. case 32:
  98. case 128:
  99. case 512:
  100. case 2048:
  101. arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle );
  102. break;
  103. }
  104. }
  105. else
  106. {
  107. switch (L)
  108. {
  109. case 16:
  110. case 64:
  111. case 256:
  112. case 1024:
  113. case 4096:
  114. arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 );
  115. break;
  116. case 32:
  117. case 128:
  118. case 512:
  119. case 2048:
  120. arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle );
  121. break;
  122. }
  123. }
  124. if( bitReverseFlag )
  125. arm_bitreversal_16((uint16_t*)p1,S->bitRevLength,S->pBitRevTable);
  126. }
  127. /**
  128. * @} end of ComplexFFT group
  129. */
  130. void arm_cfft_radix4by2_q15(
  131. q15_t * pSrc,
  132. uint32_t fftLen,
  133. const q15_t * pCoef)
  134. {
  135. uint32_t i;
  136. uint32_t n2;
  137. q15_t p0, p1, p2, p3;
  138. #ifndef ARM_MATH_CM0_FAMILY
  139. q31_t T, S, R;
  140. q31_t coeff, out1, out2;
  141. const q15_t *pC = pCoef;
  142. q15_t *pSi = pSrc;
  143. q15_t *pSl = pSrc + fftLen;
  144. #else
  145. uint32_t ia, l;
  146. q15_t xt, yt, cosVal, sinVal;
  147. #endif
  148. n2 = fftLen >> 1;
  149. #ifndef ARM_MATH_CM0_FAMILY
  150. for (i = n2; i > 0; i--)
  151. {
  152. coeff = _SIMD32_OFFSET(pC);
  153. pC += 2;
  154. T = _SIMD32_OFFSET(pSi);
  155. T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
  156. S = _SIMD32_OFFSET(pSl);
  157. S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
  158. R = __QSUB16(T, S);
  159. _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
  160. pSi += 2;
  161. #ifndef ARM_MATH_BIG_ENDIAN
  162. out1 = __SMUAD(coeff, R) >> 16;
  163. out2 = __SMUSDX(coeff, R);
  164. #else
  165. out1 = __SMUSDX(R, coeff) >> 16u;
  166. out2 = __SMUAD(coeff, R);
  167. #endif // #ifndef ARM_MATH_BIG_ENDIAN
  168. _SIMD32_OFFSET(pSl) =
  169. (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
  170. pSl += 2;
  171. }
  172. #else // #ifndef ARM_MATH_CM0_FAMILY
  173. ia = 0;
  174. for (i = 0; i < n2; i++)
  175. {
  176. cosVal = pCoef[ia * 2];
  177. sinVal = pCoef[(ia * 2) + 1];
  178. ia++;
  179. l = i + n2;
  180. xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
  181. pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
  182. yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
  183. pSrc[2 * i + 1] =
  184. ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
  185. pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
  186. ((int16_t) (((q31_t) yt * sinVal) >> 16)));
  187. pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
  188. ((int16_t) (((q31_t) xt * sinVal) >> 16)));
  189. }
  190. #endif // #ifndef ARM_MATH_CM0_FAMILY
  191. // first col
  192. arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2u);
  193. // second col
  194. arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
  195. for (i = 0; i < fftLen >> 1; i++)
  196. {
  197. p0 = pSrc[4*i+0];
  198. p1 = pSrc[4*i+1];
  199. p2 = pSrc[4*i+2];
  200. p3 = pSrc[4*i+3];
  201. p0 <<= 1;
  202. p1 <<= 1;
  203. p2 <<= 1;
  204. p3 <<= 1;
  205. pSrc[4*i+0] = p0;
  206. pSrc[4*i+1] = p1;
  207. pSrc[4*i+2] = p2;
  208. pSrc[4*i+3] = p3;
  209. }
  210. }
  211. void arm_cfft_radix4by2_inverse_q15(
  212. q15_t * pSrc,
  213. uint32_t fftLen,
  214. const q15_t * pCoef)
  215. {
  216. uint32_t i;
  217. uint32_t n2;
  218. q15_t p0, p1, p2, p3;
  219. #ifndef ARM_MATH_CM0_FAMILY
  220. q31_t T, S, R;
  221. q31_t coeff, out1, out2;
  222. const q15_t *pC = pCoef;
  223. q15_t *pSi = pSrc;
  224. q15_t *pSl = pSrc + fftLen;
  225. #else
  226. uint32_t ia, l;
  227. q15_t xt, yt, cosVal, sinVal;
  228. #endif
  229. n2 = fftLen >> 1;
  230. #ifndef ARM_MATH_CM0_FAMILY
  231. for (i = n2; i > 0; i--)
  232. {
  233. coeff = _SIMD32_OFFSET(pC);
  234. pC += 2;
  235. T = _SIMD32_OFFSET(pSi);
  236. T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
  237. S = _SIMD32_OFFSET(pSl);
  238. S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
  239. R = __QSUB16(T, S);
  240. _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
  241. pSi += 2;
  242. #ifndef ARM_MATH_BIG_ENDIAN
  243. out1 = __SMUSD(coeff, R) >> 16;
  244. out2 = __SMUADX(coeff, R);
  245. #else
  246. out1 = __SMUADX(R, coeff) >> 16u;
  247. out2 = __SMUSD(__QSUB(0, coeff), R);
  248. #endif // #ifndef ARM_MATH_BIG_ENDIAN
  249. _SIMD32_OFFSET(pSl) =
  250. (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
  251. pSl += 2;
  252. }
  253. #else // #ifndef ARM_MATH_CM0_FAMILY
  254. ia = 0;
  255. for (i = 0; i < n2; i++)
  256. {
  257. cosVal = pCoef[ia * 2];
  258. sinVal = pCoef[(ia * 2) + 1];
  259. ia++;
  260. l = i + n2;
  261. xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
  262. pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
  263. yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
  264. pSrc[2 * i + 1] =
  265. ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
  266. pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
  267. ((int16_t) (((q31_t) yt * sinVal) >> 16)));
  268. pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
  269. ((int16_t) (((q31_t) xt * sinVal) >> 16)));
  270. }
  271. #endif // #ifndef ARM_MATH_CM0_FAMILY
  272. // first col
  273. arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2u);
  274. // second col
  275. arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
  276. for (i = 0; i < fftLen >> 1; i++)
  277. {
  278. p0 = pSrc[4*i+0];
  279. p1 = pSrc[4*i+1];
  280. p2 = pSrc[4*i+2];
  281. p3 = pSrc[4*i+3];
  282. p0 <<= 1;
  283. p1 <<= 1;
  284. p2 <<= 1;
  285. p3 <<= 1;
  286. pSrc[4*i+0] = p0;
  287. pSrc[4*i+1] = p1;
  288. pSrc[4*i+2] = p2;
  289. pSrc[4*i+3] = p3;
  290. }
  291. }