armfly/User/app/dm9161/dm9161.c

/*!
    \file  gd32f4xx_enet_eval.c
    \brief ethernet hardware configuration
*/

/*
    Copyright (C) 2016 GigaDevice

    2016-08-15, V1.0.0, firmware for GD32F4xx
*/

#include "stm32f4x7_eth.h"
#include "dm9161.h"
#include "netconf.h"
#include "interface.h"
#include "lwip/sockets.h"
#include "lwip/api.h"

static __IO uint32_t enet_init_status = 0;

static void dm9161_gpio_config(void);
static void dm9161_mac_dma_config(void);
static void nvic_configuration(void);
static uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress);

/*!
    \brief      setup ethernet system(GPIOs, clocks, MAC, DMA, systick)
    \param[in]  none
    \param[out] none
    \retval     none
*/
void enet_system_setup(void)
{
    nvic_configuration();

    /* configure the GPIO ports for ethernet pins */
    dm9161_gpio_config();

    /* configure the ethernet MAC/DMA */
    dm9161_mac_dma_config();

    // /* Read PHY status register: Get Ethernet link status */
    // if (ETH_ReadPHYRegister(0x01, PHY_SR) & 1)
    // {
    //     enet_init_status |= 0x10;
    // }

    // /* Configure the PHY to generate an interrupt on change of link status */
    // Eth_Link_PHYITConfig(0x01);

    /* Configure the EXTI for Ethernet link status. */
    // Eth_Link_EXTIConfig();

    if (enet_init_status == 0)
    {
        return;
    }

    // ETH_MACITConfig(ETH_MAC_IT_PMT, ENABLE);
    ETH_DMAITConfig(ETH_DMA_IT_R, ENABLE);
    ETH_DMAITConfig(ETH_DMA_IT_NIS, ENABLE);
    // ETH_MACReceptionCmd(ENABLE);
}

/*!
    \brief      configures the ethernet interface
    \param[in]  none
    \param[out] none
    \retval     none
*/
static void dm9161_mac_dma_config(void)
{
    ErrorStatus reval_state = ERROR;

    /* reset ethernet on AHB bus */
    ETH_DeInit();

    /* Software reset */
    ETH_SoftwareReset();
    /* Wait for software reset */
    reval_state = ETH_GetSoftwareResetStatus();
    if (reval_state == ERROR)
    {
        return;
    }
    // while (ETH_GetSoftwareResetStatus() == SET)
    //     ;

    // /* ETHERNET Configuration --------------------------------------------------*/
    // /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
    ETH_InitTypeDef ETH_InitStructure;
    ETH_StructInit(&ETH_InitStructure);

    /* Fill ETH_InitStructure parametrs */
    /*------------------------   MAC   -----------------------------------*/
    ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
    //  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
    //  ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
    //  ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;

    ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
    ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
    ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
    ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
    ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
    ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
    ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
    ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
#ifdef CHECKSUM_BY_HARDWARE
    ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif

    /*------------------------   DMA   -----------------------------------------*/
    /* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
    the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
    if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
    ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
    ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
    ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;

    ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
    ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
    ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
    ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
    ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
    ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
    ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
    ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;

    /* Configure Ethernet */
    enet_init_status = ETH_Init(&ETH_InitStructure, 0x01);
}

/*!
    \brief      configures the nested vectored interrupt controller
    \param[in]  none
    \param[out] none
    \retval     none
*/
static void nvic_configuration(void)
{
    NVIC_InitTypeDef NVIC_InitStructure;
    NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
    NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
    NVIC_Init(&NVIC_InitStructure);
}

/*!
    \brief      configures the different GPIO ports
    \param[in]  none
    \param[out] none
    \retval     none
*/
static void dm9161_gpio_config(void)
{
    INT16U i = 0;
    GPIO_InitTypeDef GPIO_StructInit;
    GPIO_StructInit.GPIO_Mode = GPIO_Mode_OUT;
    // GPIO_StructInit.GPIO_OType = interface_info[index].GPIO_OType;
    GPIO_StructInit.GPIO_Speed = GPIO_High_Speed;
    GPIO_StructInit.GPIO_PuPd = GPIO_PuPd_DOWN;
    GPIO_StructInit.GPIO_Pin = ETH_RESET_PIN;
    GPIO_Init(ETH_RESET_PORT, &GPIO_StructInit);
    ETH_RESET_ON;
    while (i < 1000)
    {
        i++;
    }
    i = 0;
    ETH_RESET_OFF;
    while (i < 1000)
    {
        i++;
    }
    i = 0;
    /* Enable SYSCFG clock */
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);

#ifdef MII_MODE
#ifdef PHY_CLOCK_MCO
    /* output HXTAL clock (25MHz) on CKOUT0 pin(PA8) to clock the PHY */
    RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
#endif /* PHY_CLOCK_MCO */
    SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
#elif defined RMII_MODE
    SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
#endif
}

uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress)
{
    uint16_t tmpreg = 0;

    /* Read MICR register */
    tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_MICR);

    /* Enable output interrupt events to signal via the INT pin */
    tmpreg |= (uint16_t)(PHY_MICR_INT_EN | PHY_MICR_INT_OE);
    if (!(ETH_WritePHYRegister(PHYAddress, PHY_MICR, tmpreg)))
    {
        /* Return ERROR in case of write timeout */
        return ETH_ERROR;
    }

    /* Read MISR register */
    tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_MISR);

    /* Enable Interrupt on change of link status */
    tmpreg |= (uint16_t)PHY_MISR_LINK_INT_EN;
    if (!(ETH_WritePHYRegister(PHYAddress, PHY_MISR, tmpreg)))
    {
        /* Return ERROR in case of write timeout */
        return ETH_ERROR;
    }
    /* Return SUCCESS */
    return ETH_SUCCESS;
}

static err_t bms_net_process(int fd, void *data, int len)
{
    INT8U response[2] = {0xBB, 0xAA};
    if ((len == 2) && (((INT8U *)data)[0] == 0xAA) && (((INT8U *)data)[1] == 0xBB))
    {
        send(fd, (void *)response, sizeof(response), 0);
    }
    return 1;
}

void dm9161_task(void)
{
    INT8U buf[50];
    INT32S ret = 0;
    INT32S sockfd = -1, newfd = -1;
    INT32U len = 0;
    struct sockaddr_in svr_addr, clt_addr;

    svr_addr.sin_family = AF_INET;
    svr_addr.sin_port = htons(TCP_PORT);
    svr_addr.sin_addr.s_addr = htons(INADDR_ANY);

    while (1)
    {
        sockfd = socket(AF_INET, SOCK_STREAM, 0);
        if (sockfd < 0)
        {
            continue;
        }

        ret = bind(sockfd, (struct sockaddr *)&svr_addr, sizeof(svr_addr));
        if (ret < 0)
        {
            lwip_close(sockfd);
            sockfd = -1;
            continue;
        }

        ret = listen(sockfd, 1);
        if (ret < 0)
        {
            lwip_close(sockfd);
            continue;
        }

        len = sizeof(clt_addr);

        newfd = accept(sockfd, NULL, NULL);

        while (-1 != newfd)
        {
            ret = recv(newfd, buf, sizeof(buf) - 1, 0);
            if (ret <= 0)
            {
                lwip_close(newfd);
                newfd = -1;
                break;
            }
            bms_net_process(newfd, buf, ret);
        }

        lwip_close(sockfd);
        sockfd = -1;
        OSTimeDly(10);
    }
}