startup_stm32f446xx.s 26 KB

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  1. /**
  2. ******************************************************************************
  3. * @file startup_stm32f446xx.s
  4. * @author MCD Application Team
  5. * @version V1.5.0
  6. * @date 06-March-2015
  7. * @brief STM32F446xx Devices vector table for Atollic TrueSTUDIO toolchain.
  8. * This module performs:
  9. * - Set the initial SP
  10. * - Set the initial PC == Reset_Handler,
  11. * - Set the vector table entries with the exceptions ISR address
  12. * - Branches to main in the C library (which eventually
  13. * calls main()).
  14. * After Reset the Cortex-M4 processor is in Thread mode,
  15. * priority is Privileged, and the Stack is set to Main.
  16. ******************************************************************************
  17. * @attention
  18. *
  19. * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
  20. *
  21. * Redistribution and use in source and binary forms, with or without modification,
  22. * are permitted provided that the following conditions are met:
  23. * 1. Redistributions of source code must retain the above copyright notice,
  24. * this list of conditions and the following disclaimer.
  25. * 2. Redistributions in binary form must reproduce the above copyright notice,
  26. * this list of conditions and the following disclaimer in the documentation
  27. * and/or other materials provided with the distribution.
  28. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  29. * may be used to endorse or promote products derived from this software
  30. * without specific prior written permission.
  31. *
  32. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  36. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  38. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  39. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  40. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *
  43. ******************************************************************************
  44. */
  45. .syntax unified
  46. .cpu cortex-m4
  47. .fpu softvfp
  48. .thumb
  49. .global g_pfnVectors
  50. .global Default_Handler
  51. /* start address for the initialization values of the .data section.
  52. defined in linker script */
  53. .word _sidata
  54. /* start address for the .data section. defined in linker script */
  55. .word _sdata
  56. /* end address for the .data section. defined in linker script */
  57. .word _edata
  58. /* start address for the .bss section. defined in linker script */
  59. .word _sbss
  60. /* end address for the .bss section. defined in linker script */
  61. .word _ebss
  62. /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  63. /**
  64. * @brief This is the code that gets called when the processor first
  65. * starts execution following a reset event. Only the absolutely
  66. * necessary set is performed, after which the application
  67. * supplied main() routine is called.
  68. * @param None
  69. * @retval : None
  70. */
  71. .section .text.Reset_Handler
  72. .weak Reset_Handler
  73. .type Reset_Handler, %function
  74. Reset_Handler:
  75. ldr sp, =_estack /* set stack pointer */
  76. /* Copy the data segment initializers from flash to SRAM */
  77. movs r1, #0
  78. b LoopCopyDataInit
  79. CopyDataInit:
  80. ldr r3, =_sidata
  81. ldr r3, [r3, r1]
  82. str r3, [r0, r1]
  83. adds r1, r1, #4
  84. LoopCopyDataInit:
  85. ldr r0, =_sdata
  86. ldr r3, =_edata
  87. adds r2, r0, r1
  88. cmp r2, r3
  89. bcc CopyDataInit
  90. ldr r2, =_sbss
  91. b LoopFillZerobss
  92. /* Zero fill the bss segment. */
  93. FillZerobss:
  94. movs r3, #0
  95. str r3, [r2], #4
  96. LoopFillZerobss:
  97. ldr r3, = _ebss
  98. cmp r2, r3
  99. bcc FillZerobss
  100. /* Call the clock system intitialization function.*/
  101. bl SystemInit
  102. /* Call static constructors */
  103. bl __libc_init_array
  104. /* Call the application's entry point.*/
  105. bl main
  106. bx lr
  107. .size Reset_Handler, .-Reset_Handler
  108. /**
  109. * @brief This is the code that gets called when the processor receives an
  110. * unexpected interrupt. This simply enters an infinite loop, preserving
  111. * the system state for examination by a debugger.
  112. * @param None
  113. * @retval None
  114. */
  115. .section .text.Default_Handler,"ax",%progbits
  116. Default_Handler:
  117. Infinite_Loop:
  118. b Infinite_Loop
  119. .size Default_Handler, .-Default_Handler
  120. /******************************************************************************
  121. *
  122. * The minimal vector table for a Cortex M3. Note that the proper constructs
  123. * must be placed on this to ensure that it ends up at physical address
  124. * 0x0000.0000.
  125. *
  126. *******************************************************************************/
  127. .section .isr_vector,"a",%progbits
  128. .type g_pfnVectors, %object
  129. .size g_pfnVectors, .-g_pfnVectors
  130. g_pfnVectors:
  131. .word _estack
  132. .word Reset_Handler
  133. .word NMI_Handler
  134. .word HardFault_Handler
  135. .word MemManage_Handler
  136. .word BusFault_Handler
  137. .word UsageFault_Handler
  138. .word 0
  139. .word 0
  140. .word 0
  141. .word 0
  142. .word SVC_Handler
  143. .word DebugMon_Handler
  144. .word 0
  145. .word PendSV_Handler
  146. .word SysTick_Handler
  147. /* External Interrupts */
  148. .word WWDG_IRQHandler /* Window WatchDog */
  149. .word PVD_IRQHandler /* PVD through EXTI Line detection */
  150. .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
  151. .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
  152. .word FLASH_IRQHandler /* FLASH */
  153. .word RCC_IRQHandler /* RCC */
  154. .word EXTI0_IRQHandler /* EXTI Line0 */
  155. .word EXTI1_IRQHandler /* EXTI Line1 */
  156. .word EXTI2_IRQHandler /* EXTI Line2 */
  157. .word EXTI3_IRQHandler /* EXTI Line3 */
  158. .word EXTI4_IRQHandler /* EXTI Line4 */
  159. .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
  160. .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
  161. .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
  162. .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
  163. .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
  164. .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
  165. .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
  166. .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
  167. .word CAN1_TX_IRQHandler /* CAN1 TX */
  168. .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
  169. .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
  170. .word CAN1_SCE_IRQHandler /* CAN1 SCE */
  171. .word EXTI9_5_IRQHandler /* External Line[9:5]s */
  172. .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
  173. .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
  174. .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
  175. .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
  176. .word TIM2_IRQHandler /* TIM2 */
  177. .word TIM3_IRQHandler /* TIM3 */
  178. .word TIM4_IRQHandler /* TIM4 */
  179. .word I2C1_EV_IRQHandler /* I2C1 Event */
  180. .word I2C1_ER_IRQHandler /* I2C1 Error */
  181. .word I2C2_EV_IRQHandler /* I2C2 Event */
  182. .word I2C2_ER_IRQHandler /* I2C2 Error */
  183. .word SPI1_IRQHandler /* SPI1 */
  184. .word SPI2_IRQHandler /* SPI2 */
  185. .word USART1_IRQHandler /* USART1 */
  186. .word USART2_IRQHandler /* USART2 */
  187. .word USART3_IRQHandler /* USART3 */
  188. .word EXTI15_10_IRQHandler /* External Line[15:10]s */
  189. .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
  190. .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
  191. .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
  192. .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
  193. .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
  194. .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
  195. .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
  196. .word FMC_IRQHandler /* FMC */
  197. .word SDIO_IRQHandler /* SDIO */
  198. .word TIM5_IRQHandler /* TIM5 */
  199. .word SPI3_IRQHandler /* SPI3 */
  200. .word UART4_IRQHandler /* UART4 */
  201. .word UART5_IRQHandler /* UART5 */
  202. .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
  203. .word TIM7_IRQHandler /* TIM7 */
  204. .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
  205. .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
  206. .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
  207. .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
  208. .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
  209. .word 0 /* Reserved */
  210. .word 0 /* Reserved */
  211. .word CAN2_TX_IRQHandler /* CAN2 TX */
  212. .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
  213. .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
  214. .word CAN2_SCE_IRQHandler /* CAN2 SCE */
  215. .word OTG_FS_IRQHandler /* USB OTG FS */
  216. .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
  217. .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
  218. .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
  219. .word USART6_IRQHandler /* USART6 */
  220. .word I2C3_EV_IRQHandler /* I2C3 event */
  221. .word I2C3_ER_IRQHandler /* I2C3 error */
  222. .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
  223. .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
  224. .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
  225. .word OTG_HS_IRQHandler /* USB OTG HS */
  226. .word DCMI_IRQHandler /* DCMI */
  227. .word 0 /* Reserved */
  228. .word 0 /* Reserved */
  229. .word FPU_IRQHandler /* FPU */
  230. .word 0 /* Reserved */
  231. .word 0 /* Reserved */
  232. .word SPI4_IRQHandler /* SPI4 */
  233. .word 0 /* Reserved */
  234. .word 0 /* Reserved */
  235. .word SAI1_IRQHandler /* SAI1 */
  236. .word 0 /* Reserved */
  237. .word 0 /* Reserved */
  238. .word 0 /* Reserved */
  239. .word SAI2_IRQHandler /* SAI2 */
  240. .word QuadSPI_IRQHandler /* QuadSPI */
  241. .word CEC_IRQHandler /* CEC */
  242. .word SPDIF_RX_IRQHandler /* SPDIF RX */
  243. .word FMPI2C_Event_IRQHandler /* I2C 4 Event */
  244. .word FMPI2C_Error_IRQHandler /* I2C 4 Error */
  245. /*******************************************************************************
  246. *
  247. * Provide weak aliases for each Exception handler to the Default_Handler.
  248. * As they are weak aliases, any function with the same name will override
  249. * this definition.
  250. *
  251. *******************************************************************************/
  252. .weak NMI_Handler
  253. .thumb_set NMI_Handler,Default_Handler
  254. .weak HardFault_Handler
  255. .thumb_set HardFault_Handler,Default_Handler
  256. .weak MemManage_Handler
  257. .thumb_set MemManage_Handler,Default_Handler
  258. .weak BusFault_Handler
  259. .thumb_set BusFault_Handler,Default_Handler
  260. .weak UsageFault_Handler
  261. .thumb_set UsageFault_Handler,Default_Handler
  262. .weak SVC_Handler
  263. .thumb_set SVC_Handler,Default_Handler
  264. .weak DebugMon_Handler
  265. .thumb_set DebugMon_Handler,Default_Handler
  266. .weak PendSV_Handler
  267. .thumb_set PendSV_Handler,Default_Handler
  268. .weak SysTick_Handler
  269. .thumb_set SysTick_Handler,Default_Handler
  270. .weak WWDG_IRQHandler
  271. .thumb_set WWDG_IRQHandler,Default_Handler
  272. .weak PVD_IRQHandler
  273. .thumb_set PVD_IRQHandler,Default_Handler
  274. .weak TAMP_STAMP_IRQHandler
  275. .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
  276. .weak RTC_WKUP_IRQHandler
  277. .thumb_set RTC_WKUP_IRQHandler,Default_Handler
  278. .weak FLASH_IRQHandler
  279. .thumb_set FLASH_IRQHandler,Default_Handler
  280. .weak RCC_IRQHandler
  281. .thumb_set RCC_IRQHandler,Default_Handler
  282. .weak EXTI0_IRQHandler
  283. .thumb_set EXTI0_IRQHandler,Default_Handler
  284. .weak EXTI1_IRQHandler
  285. .thumb_set EXTI1_IRQHandler,Default_Handler
  286. .weak EXTI2_IRQHandler
  287. .thumb_set EXTI2_IRQHandler,Default_Handler
  288. .weak EXTI3_IRQHandler
  289. .thumb_set EXTI3_IRQHandler,Default_Handler
  290. .weak EXTI4_IRQHandler
  291. .thumb_set EXTI4_IRQHandler,Default_Handler
  292. .weak DMA1_Stream0_IRQHandler
  293. .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
  294. .weak DMA1_Stream1_IRQHandler
  295. .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
  296. .weak DMA1_Stream2_IRQHandler
  297. .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
  298. .weak DMA1_Stream3_IRQHandler
  299. .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
  300. .weak DMA1_Stream4_IRQHandler
  301. .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
  302. .weak DMA1_Stream5_IRQHandler
  303. .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
  304. .weak DMA1_Stream6_IRQHandler
  305. .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
  306. .weak ADC_IRQHandler
  307. .thumb_set ADC_IRQHandler,Default_Handler
  308. .weak CAN1_TX_IRQHandler
  309. .thumb_set CAN1_TX_IRQHandler,Default_Handler
  310. .weak CAN1_RX0_IRQHandler
  311. .thumb_set CAN1_RX0_IRQHandler,Default_Handler
  312. .weak CAN1_RX1_IRQHandler
  313. .thumb_set CAN1_RX1_IRQHandler,Default_Handler
  314. .weak CAN1_SCE_IRQHandler
  315. .thumb_set CAN1_SCE_IRQHandler,Default_Handler
  316. .weak EXTI9_5_IRQHandler
  317. .thumb_set EXTI9_5_IRQHandler,Default_Handler
  318. .weak TIM1_BRK_TIM9_IRQHandler
  319. .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
  320. .weak TIM1_UP_TIM10_IRQHandler
  321. .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
  322. .weak TIM1_TRG_COM_TIM11_IRQHandler
  323. .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
  324. .weak TIM1_CC_IRQHandler
  325. .thumb_set TIM1_CC_IRQHandler,Default_Handler
  326. .weak TIM2_IRQHandler
  327. .thumb_set TIM2_IRQHandler,Default_Handler
  328. .weak TIM3_IRQHandler
  329. .thumb_set TIM3_IRQHandler,Default_Handler
  330. .weak TIM4_IRQHandler
  331. .thumb_set TIM4_IRQHandler,Default_Handler
  332. .weak I2C1_EV_IRQHandler
  333. .thumb_set I2C1_EV_IRQHandler,Default_Handler
  334. .weak I2C1_ER_IRQHandler
  335. .thumb_set I2C1_ER_IRQHandler,Default_Handler
  336. .weak I2C2_EV_IRQHandler
  337. .thumb_set I2C2_EV_IRQHandler,Default_Handler
  338. .weak I2C2_ER_IRQHandler
  339. .thumb_set I2C2_ER_IRQHandler,Default_Handler
  340. .weak SPI1_IRQHandler
  341. .thumb_set SPI1_IRQHandler,Default_Handler
  342. .weak SPI2_IRQHandler
  343. .thumb_set SPI2_IRQHandler,Default_Handler
  344. .weak USART1_IRQHandler
  345. .thumb_set USART1_IRQHandler,Default_Handler
  346. .weak USART2_IRQHandler
  347. .thumb_set USART2_IRQHandler,Default_Handler
  348. .weak USART3_IRQHandler
  349. .thumb_set USART3_IRQHandler,Default_Handler
  350. .weak EXTI15_10_IRQHandler
  351. .thumb_set EXTI15_10_IRQHandler,Default_Handler
  352. .weak RTC_Alarm_IRQHandler
  353. .thumb_set RTC_Alarm_IRQHandler,Default_Handler
  354. .weak OTG_FS_WKUP_IRQHandler
  355. .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
  356. .weak TIM8_BRK_TIM12_IRQHandler
  357. .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
  358. .weak TIM8_UP_TIM13_IRQHandler
  359. .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
  360. .weak TIM8_TRG_COM_TIM14_IRQHandler
  361. .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
  362. .weak TIM8_CC_IRQHandler
  363. .thumb_set TIM8_CC_IRQHandler,Default_Handler
  364. .weak DMA1_Stream7_IRQHandler
  365. .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
  366. .weak FMC_IRQHandler
  367. .thumb_set FMC_IRQHandler,Default_Handler
  368. .weak SDIO_IRQHandler
  369. .thumb_set SDIO_IRQHandler,Default_Handler
  370. .weak TIM5_IRQHandler
  371. .thumb_set TIM5_IRQHandler,Default_Handler
  372. .weak SPI3_IRQHandler
  373. .thumb_set SPI3_IRQHandler,Default_Handler
  374. .weak UART4_IRQHandler
  375. .thumb_set UART4_IRQHandler,Default_Handler
  376. .weak UART5_IRQHandler
  377. .thumb_set UART5_IRQHandler,Default_Handler
  378. .weak TIM6_DAC_IRQHandler
  379. .thumb_set TIM6_DAC_IRQHandler,Default_Handler
  380. .weak TIM7_IRQHandler
  381. .thumb_set TIM7_IRQHandler,Default_Handler
  382. .weak DMA2_Stream0_IRQHandler
  383. .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
  384. .weak DMA2_Stream1_IRQHandler
  385. .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
  386. .weak DMA2_Stream2_IRQHandler
  387. .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
  388. .weak DMA2_Stream3_IRQHandler
  389. .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
  390. .weak DMA2_Stream4_IRQHandler
  391. .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
  392. .weak CAN2_TX_IRQHandler
  393. .thumb_set CAN2_TX_IRQHandler,Default_Handler
  394. .weak CAN2_RX0_IRQHandler
  395. .thumb_set CAN2_RX0_IRQHandler,Default_Handler
  396. .weak CAN2_RX1_IRQHandler
  397. .thumb_set CAN2_RX1_IRQHandler,Default_Handler
  398. .weak CAN2_SCE_IRQHandler
  399. .thumb_set CAN2_SCE_IRQHandler,Default_Handler
  400. .weak OTG_FS_IRQHandler
  401. .thumb_set OTG_FS_IRQHandler,Default_Handler
  402. .weak DMA2_Stream5_IRQHandler
  403. .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
  404. .weak DMA2_Stream6_IRQHandler
  405. .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
  406. .weak DMA2_Stream7_IRQHandler
  407. .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
  408. .weak USART6_IRQHandler
  409. .thumb_set USART6_IRQHandler,Default_Handler
  410. .weak I2C3_EV_IRQHandler
  411. .thumb_set I2C3_EV_IRQHandler,Default_Handler
  412. .weak I2C3_ER_IRQHandler
  413. .thumb_set I2C3_ER_IRQHandler,Default_Handler
  414. .weak OTG_HS_EP1_OUT_IRQHandler
  415. .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
  416. .weak OTG_HS_EP1_IN_IRQHandler
  417. .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
  418. .weak OTG_HS_WKUP_IRQHandler
  419. .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
  420. .weak OTG_HS_IRQHandler
  421. .thumb_set OTG_HS_IRQHandler,Default_Handler
  422. .weak DCMI_IRQHandler
  423. .thumb_set DCMI_IRQHandler,Default_Handler
  424. .weak FPU_IRQHandler
  425. .thumb_set FPU_IRQHandler,Default_Handler
  426. .weak SPI4_IRQHandler
  427. .thumb_set SPI4_IRQHandler,Default_Handler
  428. .weak SAI1_IRQHandler
  429. .thumb_set SAI1_IRQHandler,Default_Handler
  430. .weak SAI2_IRQHandler
  431. .thumb_set SAI2_IRQHandler,Default_Handler
  432. .weak QuadSPI_IRQHandler
  433. .thumb_set QuadSPI_IRQHandler,Default_Handler
  434. .weak CEC_IRQHandler
  435. .thumb_set CEC_IRQHandler,Default_Handler
  436. .weak SPDIF_RX_IRQHandler
  437. .thumb_set SPDIF_RX_IRQHandler,Default_Handler
  438. .weak FMPI2C_Event_IRQHandler
  439. .thumb_set FMPI2C_Event_IRQHandler,Default_Handler
  440. .weak FMPI2C_Error_IRQHandler
  441. .thumb_set FMPI2C_Error_IRQHandler,Default_Handler
  442. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/