stm32f4xx_rcc.h 38 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_rcc.h
  4. * @author MCD Application Team
  5. * @version V1.5.0
  6. * @date 06-March-2015
  7. * @brief This file contains all the functions prototypes for the RCC firmware library.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
  12. *
  13. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  14. * You may not use this file except in compliance with the License.
  15. * You may obtain a copy of the License at:
  16. *
  17. * http://www.st.com/software_license_agreement_liberty_v2
  18. *
  19. * Unless required by applicable law or agreed to in writing, software
  20. * distributed under the License is distributed on an "AS IS" BASIS,
  21. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  22. * See the License for the specific language governing permissions and
  23. * limitations under the License.
  24. *
  25. ******************************************************************************
  26. */
  27. /* Define to prevent recursive inclusion -------------------------------------*/
  28. #ifndef __STM32F4xx_RCC_H
  29. #define __STM32F4xx_RCC_H
  30. #ifdef __cplusplus
  31. extern "C" {
  32. #endif
  33. /* Includes ------------------------------------------------------------------*/
  34. #include "stm32f4xx.h"
  35. /** @addtogroup STM32F4xx_StdPeriph_Driver
  36. * @{
  37. */
  38. /** @addtogroup RCC
  39. * @{
  40. */
  41. /* Exported types ------------------------------------------------------------*/
  42. typedef struct
  43. {
  44. uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
  45. uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
  46. uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
  47. uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
  48. }RCC_ClocksTypeDef;
  49. /* Exported constants --------------------------------------------------------*/
  50. /** @defgroup RCC_Exported_Constants
  51. * @{
  52. */
  53. /** @defgroup RCC_HSE_configuration
  54. * @{
  55. */
  56. #define RCC_HSE_OFF ((uint8_t)0x00)
  57. #define RCC_HSE_ON ((uint8_t)0x01)
  58. #define RCC_HSE_Bypass ((uint8_t)0x05)
  59. #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
  60. ((HSE) == RCC_HSE_Bypass))
  61. /**
  62. * @}
  63. */
  64. /** @defgroup RCC_LSE_Dual_Mode_Selection
  65. * @{
  66. */
  67. #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
  68. #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
  69. #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
  70. ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
  71. /**
  72. * @}
  73. */
  74. /** @defgroup RCC_PLLSAIDivR_Factor
  75. * @{
  76. */
  77. #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
  78. #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
  79. #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
  80. #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
  81. #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
  82. ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
  83. ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
  84. ((VALUE) == RCC_PLLSAIDivR_Div16))
  85. /**
  86. * @}
  87. */
  88. /** @defgroup RCC_PLL_Clock_Source
  89. * @{
  90. */
  91. #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
  92. #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
  93. #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
  94. ((SOURCE) == RCC_PLLSource_HSE))
  95. #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
  96. #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
  97. #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
  98. #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
  99. #if defined(STM32F446xx)
  100. #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
  101. #endif /* STM32F446xx */
  102. #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
  103. #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
  104. #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
  105. #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
  106. #if defined(STM32F446xx)
  107. #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
  108. #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
  109. #endif /* STM32F446xx */
  110. #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
  111. #if defined(STM32F446xx)
  112. #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
  113. #endif /* STM32F446xx */
  114. #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
  115. #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
  116. #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
  117. #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
  118. /**
  119. * @}
  120. */
  121. /** @defgroup RCC_System_Clock_Source
  122. * @{
  123. */
  124. #if defined(STM32F446xx)
  125. #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
  126. #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
  127. #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
  128. #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
  129. #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
  130. ((SOURCE) == RCC_SYSCLKSource_HSE) || \
  131. ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
  132. ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
  133. /* Add legacy definition */
  134. #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
  135. #endif /* STM32F446xx */
  136. #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
  137. #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
  138. #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
  139. #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
  140. #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
  141. ((SOURCE) == RCC_SYSCLKSource_HSE) || \
  142. ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
  143. #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
  144. /**
  145. * @}
  146. */
  147. /** @defgroup RCC_AHB_Clock_Source
  148. * @{
  149. */
  150. #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
  151. #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
  152. #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
  153. #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
  154. #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
  155. #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
  156. #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
  157. #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
  158. #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
  159. #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
  160. ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
  161. ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
  162. ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
  163. ((HCLK) == RCC_SYSCLK_Div512))
  164. /**
  165. * @}
  166. */
  167. /** @defgroup RCC_APB1_APB2_Clock_Source
  168. * @{
  169. */
  170. #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
  171. #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
  172. #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
  173. #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
  174. #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
  175. #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
  176. ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
  177. ((PCLK) == RCC_HCLK_Div16))
  178. /**
  179. * @}
  180. */
  181. /** @defgroup RCC_Interrupt_Source
  182. * @{
  183. */
  184. #define RCC_IT_LSIRDY ((uint8_t)0x01)
  185. #define RCC_IT_LSERDY ((uint8_t)0x02)
  186. #define RCC_IT_HSIRDY ((uint8_t)0x04)
  187. #define RCC_IT_HSERDY ((uint8_t)0x08)
  188. #define RCC_IT_PLLRDY ((uint8_t)0x10)
  189. #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
  190. #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
  191. #define RCC_IT_CSS ((uint8_t)0x80)
  192. #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
  193. #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
  194. ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
  195. ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
  196. ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
  197. #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
  198. /**
  199. * @}
  200. */
  201. /** @defgroup RCC_LSE_Configuration
  202. * @{
  203. */
  204. #define RCC_LSE_OFF ((uint8_t)0x00)
  205. #define RCC_LSE_ON ((uint8_t)0x01)
  206. #define RCC_LSE_Bypass ((uint8_t)0x04)
  207. #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
  208. ((LSE) == RCC_LSE_Bypass))
  209. /**
  210. * @}
  211. */
  212. /** @defgroup RCC_RTC_Clock_Source
  213. * @{
  214. */
  215. #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
  216. #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
  217. #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
  218. #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
  219. #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
  220. #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
  221. #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
  222. #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
  223. #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
  224. #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
  225. #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
  226. #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
  227. #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
  228. #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
  229. #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
  230. #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
  231. #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
  232. #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
  233. #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
  234. #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
  235. #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
  236. #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
  237. #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
  238. #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
  239. #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
  240. #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
  241. #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
  242. #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
  243. #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
  244. #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
  245. #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
  246. #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
  247. #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
  248. ((SOURCE) == RCC_RTCCLKSource_LSI) || \
  249. ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
  250. ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
  251. ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
  252. ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
  253. ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
  254. ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
  255. ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
  256. ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
  257. ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
  258. ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
  259. ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
  260. ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
  261. ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
  262. ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
  263. ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
  264. ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
  265. ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
  266. ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
  267. ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
  268. ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
  269. ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
  270. ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
  271. ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
  272. ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
  273. ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
  274. ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
  275. ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
  276. ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
  277. ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
  278. ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
  279. /**
  280. * @}
  281. */
  282. #if defined(STM32F446xx)
  283. /** @defgroup RCC_I2S_Clock_Source
  284. * @{
  285. */
  286. #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
  287. #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
  288. #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
  289. #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
  290. #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
  291. ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
  292. /**
  293. * @}
  294. */
  295. /** @defgroup RCC_I2S_APBBus
  296. * @{
  297. */
  298. #define RCC_I2SBus_APB1 ((uint8_t)0x00)
  299. #define RCC_I2SBus_APB2 ((uint8_t)0x01)
  300. #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
  301. /**
  302. * @}
  303. */
  304. /** @defgroup RCC_SAI_Clock_Source
  305. * @{
  306. */
  307. #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
  308. #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
  309. #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
  310. #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
  311. #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
  312. ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
  313. /**
  314. * @}
  315. */
  316. /** @defgroup RCC_SAI_Instance
  317. * @{
  318. */
  319. #define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
  320. #define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
  321. #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
  322. /**
  323. * @}
  324. */
  325. #endif /* STM32F446xx */
  326. #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
  327. /** @defgroup RCC_I2S_Clock_Source
  328. * @{
  329. */
  330. #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
  331. #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
  332. #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
  333. /**
  334. * @}
  335. */
  336. /** @defgroup RCC_SAI_BlockA_Clock_Source
  337. * @{
  338. */
  339. #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
  340. #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
  341. #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
  342. #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
  343. ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
  344. ((SOURCE) == RCC_SAIACLKSource_Ext))
  345. /**
  346. * @}
  347. */
  348. /** @defgroup RCC_SAI_BlockB_Clock_Source
  349. * @{
  350. */
  351. #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
  352. #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
  353. #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
  354. #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
  355. ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
  356. ((SOURCE) == RCC_SAIBCLKSource_Ext))
  357. /**
  358. * @}
  359. */
  360. #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
  361. /** @defgroup RCC_TIM_PRescaler_Selection
  362. * @{
  363. */
  364. #define RCC_TIMPrescDesactivated ((uint8_t)0x00)
  365. #define RCC_TIMPrescActivated ((uint8_t)0x01)
  366. #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
  367. /**
  368. * @}
  369. */
  370. #if defined(STM32F446xx)
  371. /** @defgroup RCC_SDIO_Clock_Source_Selection
  372. * @{
  373. */
  374. #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
  375. #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
  376. #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
  377. ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
  378. /**
  379. * @}
  380. */
  381. /** @defgroup RCC_48MHZ_Clock_Source_Selection
  382. * @{
  383. */
  384. #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
  385. #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
  386. #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
  387. ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
  388. /**
  389. * @}
  390. */
  391. #endif /* STM32F446xx */
  392. #if defined(STM32F446xx)
  393. /** @defgroup RCC_SPDIFRX_Clock_Source_Selection
  394. * @{
  395. */
  396. #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
  397. #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
  398. #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
  399. ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
  400. /**
  401. * @}
  402. */
  403. /** @defgroup RCC_CEC_Clock_Source_Selection
  404. * @{
  405. */
  406. #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
  407. #define RCC_CECCLKSource_LSE ((uint8_t)0x01)
  408. #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
  409. ((CLKSOURCE) == RCC_CECCLKSource_LSE))
  410. /**
  411. * @}
  412. */
  413. /** @defgroup RCC_FMPI2C1_Clock_Source
  414. * @{
  415. */
  416. #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
  417. #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
  418. #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
  419. #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
  420. ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
  421. /**
  422. * @}
  423. */
  424. /** @defgroup RCC_AHB1_ClockGating
  425. * @{
  426. */
  427. #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
  428. #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
  429. #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
  430. #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
  431. #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
  432. #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
  433. #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
  434. #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
  435. /**
  436. * @}
  437. */
  438. #endif /* STM32F446xx */
  439. /** @defgroup RCC_AHB1_Peripherals
  440. * @{
  441. */
  442. #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
  443. #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
  444. #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
  445. #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
  446. #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
  447. #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
  448. #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
  449. #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
  450. #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
  451. #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
  452. #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
  453. #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
  454. #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
  455. #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
  456. #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
  457. #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
  458. #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
  459. #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
  460. #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
  461. #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
  462. #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
  463. #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
  464. #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
  465. #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
  466. #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
  467. #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
  468. #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
  469. #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
  470. #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
  471. #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
  472. /**
  473. * @}
  474. */
  475. /** @defgroup RCC_AHB2_Peripherals
  476. * @{
  477. */
  478. #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
  479. #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
  480. #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
  481. #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
  482. #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
  483. #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
  484. /**
  485. * @}
  486. */
  487. /** @defgroup RCC_AHB3_Peripherals
  488. * @{
  489. */
  490. #if defined(STM32F40_41xxx)
  491. #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
  492. #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
  493. #endif /* STM32F40_41xxx */
  494. #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
  495. #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
  496. #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
  497. #endif /* STM32F427_437xx || STM32F429_439xx */
  498. #if defined(STM32F446xx)
  499. #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
  500. #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
  501. #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
  502. #endif /* STM32F446xx */
  503. /**
  504. * @}
  505. */
  506. /** @defgroup RCC_APB1_Peripherals
  507. * @{
  508. */
  509. #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
  510. #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
  511. #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
  512. #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
  513. #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
  514. #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
  515. #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
  516. #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
  517. #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
  518. #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
  519. #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
  520. #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
  521. #if defined(STM32F446xx)
  522. #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
  523. #endif /* STM32F446xx */
  524. #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
  525. #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
  526. #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
  527. #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
  528. #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
  529. #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
  530. #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
  531. #if defined(STM32F446xx)
  532. #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
  533. #endif /* STM32F446xx */
  534. #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
  535. #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
  536. #if defined(STM32F446xx)
  537. #define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
  538. #endif /* STM32F446xx */
  539. #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
  540. #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
  541. #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
  542. #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
  543. #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
  544. /**
  545. * @}
  546. */
  547. /** @defgroup RCC_APB2_Peripherals
  548. * @{
  549. */
  550. #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
  551. #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
  552. #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
  553. #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
  554. #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
  555. #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
  556. #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
  557. #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
  558. #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
  559. #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
  560. #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
  561. #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
  562. #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
  563. #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
  564. #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
  565. #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
  566. #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
  567. #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
  568. #if defined(STM32F446xx)
  569. #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
  570. #endif /* STM32F446xx */
  571. #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
  572. #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00))
  573. #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00))
  574. /**
  575. * @}
  576. */
  577. /** @defgroup RCC_MCO1_Clock_Source_Prescaler
  578. * @{
  579. */
  580. #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
  581. #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
  582. #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
  583. #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
  584. #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
  585. #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
  586. #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
  587. #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
  588. #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
  589. #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
  590. ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
  591. #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
  592. ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
  593. ((DIV) == RCC_MCO1Div_5))
  594. /**
  595. * @}
  596. */
  597. /** @defgroup RCC_MCO2_Clock_Source_Prescaler
  598. * @{
  599. */
  600. #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
  601. #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
  602. #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
  603. #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
  604. #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
  605. #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
  606. #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
  607. #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
  608. #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
  609. #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
  610. ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
  611. #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
  612. ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
  613. ((DIV) == RCC_MCO2Div_5))
  614. /**
  615. * @}
  616. */
  617. /** @defgroup RCC_Flag
  618. * @{
  619. */
  620. #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
  621. #define RCC_FLAG_HSERDY ((uint8_t)0x31)
  622. #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
  623. #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
  624. #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
  625. #define RCC_FLAG_LSERDY ((uint8_t)0x41)
  626. #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
  627. #define RCC_FLAG_BORRST ((uint8_t)0x79)
  628. #define RCC_FLAG_PINRST ((uint8_t)0x7A)
  629. #define RCC_FLAG_PORRST ((uint8_t)0x7B)
  630. #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
  631. #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
  632. #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
  633. #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
  634. #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
  635. ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
  636. ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
  637. ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
  638. ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
  639. ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
  640. ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
  641. #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
  642. /**
  643. * @}
  644. */
  645. /**
  646. * @}
  647. */
  648. /* Exported macro ------------------------------------------------------------*/
  649. /* Exported functions --------------------------------------------------------*/
  650. /* Function used to set the RCC clock configuration to the default reset state */
  651. void RCC_DeInit(void);
  652. /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
  653. void RCC_HSEConfig(uint8_t RCC_HSE);
  654. ErrorStatus RCC_WaitForHSEStartUp(void);
  655. void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
  656. void RCC_HSICmd(FunctionalState NewState);
  657. void RCC_LSEConfig(uint8_t RCC_LSE);
  658. void RCC_LSICmd(FunctionalState NewState);
  659. void RCC_PLLCmd(FunctionalState NewState);
  660. #if defined(STM32F446xx)
  661. void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
  662. #endif /* STM32F446xx */
  663. #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
  664. void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
  665. #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
  666. void RCC_PLLI2SCmd(FunctionalState NewState);
  667. #if defined(STM32F40_41xxx) || defined(STM32F401xx)
  668. void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
  669. #endif /* STM32F40_41xxx || STM32F401xx */
  670. #if defined(STM32F411xE)
  671. void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
  672. #endif /* STM32F411xE */
  673. #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
  674. void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
  675. #endif /* STM32F427_437xx || STM32F429_439xx */
  676. #if defined(STM32F446xx)
  677. void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
  678. #endif /* STM32F446xx */
  679. void RCC_PLLSAICmd(FunctionalState NewState);
  680. #if defined(STM32F446xx)
  681. void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
  682. #endif /* STM32F446xx */
  683. #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
  684. void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
  685. #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
  686. void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
  687. void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
  688. void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
  689. /* System, AHB and APB busses clocks configuration functions ******************/
  690. void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
  691. uint8_t RCC_GetSYSCLKSource(void);
  692. void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
  693. void RCC_PCLK1Config(uint32_t RCC_HCLK);
  694. void RCC_PCLK2Config(uint32_t RCC_HCLK);
  695. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
  696. /* Peripheral clocks configuration functions **********************************/
  697. void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
  698. void RCC_RTCCLKCmd(FunctionalState NewState);
  699. void RCC_BackupResetCmd(FunctionalState NewState);
  700. #if defined(STM32F446xx)
  701. void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
  702. void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
  703. #endif /* STM32F446xx */
  704. #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
  705. void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
  706. void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
  707. void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
  708. #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
  709. void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
  710. void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
  711. void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
  712. void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
  713. void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
  714. void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
  715. void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
  716. void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
  717. void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
  718. void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
  719. void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
  720. void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
  721. void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
  722. void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
  723. void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
  724. void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
  725. void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
  726. void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
  727. void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
  728. /* Features available only for STM32F411xx/STM32F446xx devices */
  729. void RCC_LSEModeConfig(uint8_t RCC_Mode);
  730. /* Features available only for STM32F446xx devices */
  731. #if defined(STM32F446xx)
  732. void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
  733. void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
  734. #endif /* STM32F446xx */
  735. /* Features available only for STM32F446xx devices */
  736. #if defined(STM32F446xx)
  737. void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
  738. void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
  739. void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
  740. void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
  741. #endif /* STM32F446xx */
  742. /* Interrupts and flags management functions **********************************/
  743. void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
  744. FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
  745. void RCC_ClearFlag(void);
  746. ITStatus RCC_GetITStatus(uint8_t RCC_IT);
  747. void RCC_ClearITPendingBit(uint8_t RCC_IT);
  748. #ifdef __cplusplus
  749. }
  750. #endif
  751. #endif /* __STM32F4xx_RCC_H */
  752. /**
  753. * @}
  754. */
  755. /**
  756. * @}
  757. */
  758. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/