arm_power_q31.c 4.8 KB

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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_power_q31.c
  9. *
  10. * Description: Sum of the squares of the elements of a Q31 vector.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupStats
  43. */
  44. /**
  45. * @addtogroup power
  46. * @{
  47. */
  48. /**
  49. * @brief Sum of the squares of the elements of a Q31 vector.
  50. * @param[in] *pSrc points to the input vector
  51. * @param[in] blockSize length of the input vector
  52. * @param[out] *pResult sum of the squares value returned here
  53. * @return none.
  54. *
  55. * @details
  56. * <b>Scaling and Overflow Behavior:</b>
  57. *
  58. * \par
  59. * The function is implemented using a 64-bit internal accumulator.
  60. * The input is represented in 1.31 format.
  61. * Intermediate multiplication yields a 2.62 format, and this
  62. * result is truncated to 2.48 format by discarding the lower 14 bits.
  63. * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
  64. * With 15 guard bits in the accumulator, there is no risk of overflow, and the
  65. * full precision of the intermediate multiplication is preserved.
  66. * Finally, the return result is in 16.48 format.
  67. *
  68. */
  69. void arm_power_q31(
  70. q31_t * pSrc,
  71. uint32_t blockSize,
  72. q63_t * pResult)
  73. {
  74. q63_t sum = 0; /* Temporary result storage */
  75. q31_t in;
  76. uint32_t blkCnt; /* loop counter */
  77. #ifndef ARM_MATH_CM0_FAMILY
  78. /* Run the below code for Cortex-M4 and Cortex-M3 */
  79. /*loop Unrolling */
  80. blkCnt = blockSize >> 2u;
  81. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  82. ** a second loop below computes the remaining 1 to 3 samples. */
  83. while(blkCnt > 0u)
  84. {
  85. /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
  86. /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
  87. in = *pSrc++;
  88. sum += ((q63_t) in * in) >> 14u;
  89. in = *pSrc++;
  90. sum += ((q63_t) in * in) >> 14u;
  91. in = *pSrc++;
  92. sum += ((q63_t) in * in) >> 14u;
  93. in = *pSrc++;
  94. sum += ((q63_t) in * in) >> 14u;
  95. /* Decrement the loop counter */
  96. blkCnt--;
  97. }
  98. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
  99. ** No loop unrolling is used. */
  100. blkCnt = blockSize % 0x4u;
  101. #else
  102. /* Run the below code for Cortex-M0 */
  103. /* Loop over blockSize number of values */
  104. blkCnt = blockSize;
  105. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  106. while(blkCnt > 0u)
  107. {
  108. /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
  109. /* Compute Power and then store the result in a temporary variable, sum. */
  110. in = *pSrc++;
  111. sum += ((q63_t) in * in) >> 14u;
  112. /* Decrement the loop counter */
  113. blkCnt--;
  114. }
  115. /* Store the results in 16.48 format */
  116. *pResult = sum;
  117. }
  118. /**
  119. * @} end of power group
  120. */