arm_mult_q15.c 5.0 KB

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  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_mult_q15.c
  9. *
  10. * Description: Q15 vector multiplication.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * -------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @ingroup groupMath
  43. */
  44. /**
  45. * @addtogroup BasicMult
  46. * @{
  47. */
  48. /**
  49. * @brief Q15 vector multiplication
  50. * @param[in] *pSrcA points to the first input vector
  51. * @param[in] *pSrcB points to the second input vector
  52. * @param[out] *pDst points to the output vector
  53. * @param[in] blockSize number of samples in each vector
  54. * @return none.
  55. *
  56. * <b>Scaling and Overflow Behavior:</b>
  57. * \par
  58. * The function uses saturating arithmetic.
  59. * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
  60. */
  61. void arm_mult_q15(
  62. q15_t * pSrcA,
  63. q15_t * pSrcB,
  64. q15_t * pDst,
  65. uint32_t blockSize)
  66. {
  67. uint32_t blkCnt; /* loop counters */
  68. #ifndef ARM_MATH_CM0_FAMILY
  69. /* Run the below code for Cortex-M4 and Cortex-M3 */
  70. q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
  71. q15_t out1, out2, out3, out4; /* temporary output variables */
  72. q31_t mul1, mul2, mul3, mul4; /* temporary variables */
  73. /* loop Unrolling */
  74. blkCnt = blockSize >> 2u;
  75. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
  76. ** a second loop below computes the remaining 1 to 3 samples. */
  77. while(blkCnt > 0u)
  78. {
  79. /* read two samples at a time from sourceA */
  80. inA1 = *__SIMD32(pSrcA)++;
  81. /* read two samples at a time from sourceB */
  82. inB1 = *__SIMD32(pSrcB)++;
  83. /* read two samples at a time from sourceA */
  84. inA2 = *__SIMD32(pSrcA)++;
  85. /* read two samples at a time from sourceB */
  86. inB2 = *__SIMD32(pSrcB)++;
  87. /* multiply mul = sourceA * sourceB */
  88. mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
  89. mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
  90. mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
  91. mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
  92. /* saturate result to 16 bit */
  93. out1 = (q15_t) __SSAT(mul1 >> 15, 16);
  94. out2 = (q15_t) __SSAT(mul2 >> 15, 16);
  95. out3 = (q15_t) __SSAT(mul3 >> 15, 16);
  96. out4 = (q15_t) __SSAT(mul4 >> 15, 16);
  97. /* store the result */
  98. #ifndef ARM_MATH_BIG_ENDIAN
  99. *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
  100. *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
  101. #else
  102. *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
  103. *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
  104. #endif // #ifndef ARM_MATH_BIG_ENDIAN
  105. /* Decrement the blockSize loop counter */
  106. blkCnt--;
  107. }
  108. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
  109. ** No loop unrolling is used. */
  110. blkCnt = blockSize % 0x4u;
  111. #else
  112. /* Run the below code for Cortex-M0 */
  113. /* Initialize blkCnt with number of samples */
  114. blkCnt = blockSize;
  115. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  116. while(blkCnt > 0u)
  117. {
  118. /* C = A * B */
  119. /* Multiply the inputs and store the result in the destination buffer */
  120. *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
  121. /* Decrement the blockSize loop counter */
  122. blkCnt--;
  123. }
  124. }
  125. /**
  126. * @} end of BasicMult group
  127. */