arm_rms_q31.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150
  1. /* ----------------------------------------------------------------------
  2. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
  3. *
  4. * $Date: 12. March 2014
  5. * $Revision: V1.4.4
  6. *
  7. * Project: CMSIS DSP Library
  8. * Title: arm_rms_q31.c
  9. *
  10. * Description: Root Mean Square of the elements of a Q31 vector.
  11. *
  12. * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions
  16. * are met:
  17. * - Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. * - Neither the name of ARM LIMITED nor the names of its contributors
  24. * may be used to endorse or promote products derived from this
  25. * software without specific prior written permission.
  26. *
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. * ---------------------------------------------------------------------------- */
  40. #include "arm_math.h"
  41. /**
  42. * @addtogroup RMS
  43. * @{
  44. */
  45. /**
  46. * @brief Root Mean Square of the elements of a Q31 vector.
  47. * @param[in] *pSrc points to the input vector
  48. * @param[in] blockSize length of the input vector
  49. * @param[out] *pResult rms value returned here
  50. * @return none.
  51. *
  52. * @details
  53. * <b>Scaling and Overflow Behavior:</b>
  54. *
  55. *\par
  56. * The function is implemented using an internal 64-bit accumulator.
  57. * The input is represented in 1.31 format, and intermediate multiplication
  58. * yields a 2.62 format.
  59. * The accumulator maintains full precision of the intermediate multiplication results,
  60. * but provides only a single guard bit.
  61. * There is no saturation on intermediate additions.
  62. * If the accumulator overflows, it wraps around and distorts the result.
  63. * In order to avoid overflows completely, the input signal must be scaled down by
  64. * log2(blockSize) bits, as a total of blockSize additions are performed internally.
  65. * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
  66. *
  67. */
  68. void arm_rms_q31(
  69. q31_t * pSrc,
  70. uint32_t blockSize,
  71. q31_t * pResult)
  72. {
  73. q63_t sum = 0; /* accumulator */
  74. q31_t in; /* Temporary variable to store the input */
  75. uint32_t blkCnt; /* loop counter */
  76. #ifndef ARM_MATH_CM0_FAMILY
  77. /* Run the below code for Cortex-M4 and Cortex-M3 */
  78. q31_t in1, in2, in3, in4; /* Temporary input variables */
  79. /*loop Unrolling */
  80. blkCnt = blockSize >> 2u;
  81. /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
  82. ** a second loop below computes the remaining 1 to 7 samples. */
  83. while(blkCnt > 0u)
  84. {
  85. /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
  86. /* Compute sum of the squares and then store the result in a temporary variable, sum */
  87. /* read two samples from source buffer */
  88. in1 = pSrc[0];
  89. in2 = pSrc[1];
  90. /* calculate power and accumulate to accumulator */
  91. sum += (q63_t) in1 *in1;
  92. sum += (q63_t) in2 *in2;
  93. /* read two samples from source buffer */
  94. in3 = pSrc[2];
  95. in4 = pSrc[3];
  96. /* calculate power and accumulate to accumulator */
  97. sum += (q63_t) in3 *in3;
  98. sum += (q63_t) in4 *in4;
  99. /* update source buffer to process next samples */
  100. pSrc += 4u;
  101. /* Decrement the loop counter */
  102. blkCnt--;
  103. }
  104. /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
  105. ** No loop unrolling is used. */
  106. blkCnt = blockSize % 0x4u;
  107. #else
  108. /* Run the below code for Cortex-M0 */
  109. blkCnt = blockSize;
  110. #endif /* #ifndef ARM_MATH_CM0_FAMILY */
  111. while(blkCnt > 0u)
  112. {
  113. /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
  114. /* Compute sum of the squares and then store the results in a temporary variable, sum */
  115. in = *pSrc++;
  116. sum += (q63_t) in *in;
  117. /* Decrement the loop counter */
  118. blkCnt--;
  119. }
  120. /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
  121. /* Compute Rms and store the result in the destination vector */
  122. arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
  123. }
  124. /**
  125. * @} end of RMS group
  126. */