| CMSIS-CORE Version 4.00 CMSIS-CORE support for Cortex-M processor-based devices

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CoreDebug_Type Struct Reference

Structure type to access the Core Debug Register (CoreDebug).

## Data Fields

__IO uint32_t | DHCSR
| Offset: 0x000 (R/W) Debug Halting Control and Status Register.
__O uint32_t | DCRSR
| Offset: 0x004 ( /W) Debug Core Register Selector Register.
__IO uint32_t | DCRDR
| Offset: 0x008 (R/W) Debug Core Register Data Register.
__IO uint32_t | DEMCR
| Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.

## Field Documentation

__IO uint32_t CoreDebug_Type::DCRDR

__O uint32_t CoreDebug_Type::DCRSR

__IO uint32_t CoreDebug_Type::DEMCR

__IO uint32_t CoreDebug_Type::DHCSR