core_cmInstr.h 25 KB

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  1. /**************************************************************************//**
  2. * @file core_cmInstr.h
  3. * @brief CMSIS Cortex-M Core Instruction Access Header File
  4. * @version V4.00
  5. * @date 28. August 2014
  6. *
  7. * @note
  8. *
  9. ******************************************************************************/
  10. /* Copyright (c) 2009 - 2014 ARM LIMITED
  11. All rights reserved.
  12. Redistribution and use in source and binary forms, with or without
  13. modification, are permitted provided that the following conditions are met:
  14. - Redistributions of source code must retain the above copyright
  15. notice, this list of conditions and the following disclaimer.
  16. - Redistributions in binary form must reproduce the above copyright
  17. notice, this list of conditions and the following disclaimer in the
  18. documentation and/or other materials provided with the distribution.
  19. - Neither the name of ARM nor the names of its contributors may be used
  20. to endorse or promote products derived from this software without
  21. specific prior written permission.
  22. *
  23. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26. ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  27. LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28. CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29. SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30. INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31. CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  33. POSSIBILITY OF SUCH DAMAGE.
  34. ---------------------------------------------------------------------------*/
  35. #ifndef __CORE_CMINSTR_H
  36. #define __CORE_CMINSTR_H
  37. /* ########################## Core Instruction Access ######################### */
  38. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  39. Access to dedicated instructions
  40. @{
  41. */
  42. #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
  43. /* ARM armcc specific functions */
  44. #if (__ARMCC_VERSION < 400677)
  45. #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  46. #endif
  47. /** \brief No Operation
  48. No Operation does nothing. This instruction can be used for code alignment purposes.
  49. */
  50. #define __NOP __nop
  51. /** \brief Wait For Interrupt
  52. Wait For Interrupt is a hint instruction that suspends execution
  53. until one of a number of events occurs.
  54. */
  55. #define __WFI __wfi
  56. /** \brief Wait For Event
  57. Wait For Event is a hint instruction that permits the processor to enter
  58. a low-power state until one of a number of events occurs.
  59. */
  60. #define __WFE __wfe
  61. /** \brief Send Event
  62. Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  63. */
  64. #define __SEV __sev
  65. /** \brief Instruction Synchronization Barrier
  66. Instruction Synchronization Barrier flushes the pipeline in the processor,
  67. so that all instructions following the ISB are fetched from cache or
  68. memory, after the instruction has been completed.
  69. */
  70. #define __ISB() __isb(0xF)
  71. /** \brief Data Synchronization Barrier
  72. This function acts as a special kind of Data Memory Barrier.
  73. It completes when all explicit memory accesses before this instruction complete.
  74. */
  75. #define __DSB() __dsb(0xF)
  76. /** \brief Data Memory Barrier
  77. This function ensures the apparent order of the explicit memory operations before
  78. and after the instruction, without ensuring their completion.
  79. */
  80. #define __DMB() __dmb(0xF)
  81. /** \brief Reverse byte order (32 bit)
  82. This function reverses the byte order in integer value.
  83. \param [in] value Value to reverse
  84. \return Reversed value
  85. */
  86. #define __REV __rev
  87. /** \brief Reverse byte order (16 bit)
  88. This function reverses the byte order in two unsigned short values.
  89. \param [in] value Value to reverse
  90. \return Reversed value
  91. */
  92. #ifndef __NO_EMBEDDED_ASM
  93. __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
  94. {
  95. rev16 r0, r0
  96. bx lr
  97. }
  98. #endif
  99. /** \brief Reverse byte order in signed short value
  100. This function reverses the byte order in a signed short value with sign extension to integer.
  101. \param [in] value Value to reverse
  102. \return Reversed value
  103. */
  104. #ifndef __NO_EMBEDDED_ASM
  105. __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
  106. {
  107. revsh r0, r0
  108. bx lr
  109. }
  110. #endif
  111. /** \brief Rotate Right in unsigned value (32 bit)
  112. This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  113. \param [in] value Value to rotate
  114. \param [in] value Number of Bits to rotate
  115. \return Rotated value
  116. */
  117. #define __ROR __ror
  118. /** \brief Breakpoint
  119. This function causes the processor to enter Debug state.
  120. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  121. \param [in] value is ignored by the processor.
  122. If required, a debugger can use it to store additional information about the breakpoint.
  123. */
  124. #define __BKPT(value) __breakpoint(value)
  125. #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
  126. /** \brief Reverse bit order of value
  127. This function reverses the bit order of the given value.
  128. \param [in] value Value to reverse
  129. \return Reversed value
  130. */
  131. #define __RBIT __rbit
  132. /** \brief LDR Exclusive (8 bit)
  133. This function executes a exclusive LDR instruction for 8 bit value.
  134. \param [in] ptr Pointer to data
  135. \return value of type uint8_t at (*ptr)
  136. */
  137. #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
  138. /** \brief LDR Exclusive (16 bit)
  139. This function executes a exclusive LDR instruction for 16 bit values.
  140. \param [in] ptr Pointer to data
  141. \return value of type uint16_t at (*ptr)
  142. */
  143. #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
  144. /** \brief LDR Exclusive (32 bit)
  145. This function executes a exclusive LDR instruction for 32 bit values.
  146. \param [in] ptr Pointer to data
  147. \return value of type uint32_t at (*ptr)
  148. */
  149. #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
  150. /** \brief STR Exclusive (8 bit)
  151. This function executes a exclusive STR instruction for 8 bit values.
  152. \param [in] value Value to store
  153. \param [in] ptr Pointer to location
  154. \return 0 Function succeeded
  155. \return 1 Function failed
  156. */
  157. #define __STREXB(value, ptr) __strex(value, ptr)
  158. /** \brief STR Exclusive (16 bit)
  159. This function executes a exclusive STR instruction for 16 bit values.
  160. \param [in] value Value to store
  161. \param [in] ptr Pointer to location
  162. \return 0 Function succeeded
  163. \return 1 Function failed
  164. */
  165. #define __STREXH(value, ptr) __strex(value, ptr)
  166. /** \brief STR Exclusive (32 bit)
  167. This function executes a exclusive STR instruction for 32 bit values.
  168. \param [in] value Value to store
  169. \param [in] ptr Pointer to location
  170. \return 0 Function succeeded
  171. \return 1 Function failed
  172. */
  173. #define __STREXW(value, ptr) __strex(value, ptr)
  174. /** \brief Remove the exclusive lock
  175. This function removes the exclusive lock which is created by LDREX.
  176. */
  177. #define __CLREX __clrex
  178. /** \brief Signed Saturate
  179. This function saturates a signed value.
  180. \param [in] value Value to be saturated
  181. \param [in] sat Bit position to saturate to (1..32)
  182. \return Saturated value
  183. */
  184. #define __SSAT __ssat
  185. /** \brief Unsigned Saturate
  186. This function saturates an unsigned value.
  187. \param [in] value Value to be saturated
  188. \param [in] sat Bit position to saturate to (0..31)
  189. \return Saturated value
  190. */
  191. #define __USAT __usat
  192. /** \brief Count leading zeros
  193. This function counts the number of leading zeros of a data value.
  194. \param [in] value Value to count the leading zeros
  195. \return number of leading zeros in value
  196. */
  197. #define __CLZ __clz
  198. /** \brief Rotate Right with Extend (32 bit)
  199. This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
  200. \param [in] value Value to rotate
  201. \return Rotated value
  202. */
  203. #ifndef __NO_EMBEDDED_ASM
  204. __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
  205. {
  206. rrx r0, r0
  207. bx lr
  208. }
  209. #endif
  210. /** \brief LDRT Unprivileged (8 bit)
  211. This function executes a Unprivileged LDRT instruction for 8 bit value.
  212. \param [in] ptr Pointer to data
  213. \return value of type uint8_t at (*ptr)
  214. */
  215. #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
  216. /** \brief LDRT Unprivileged (16 bit)
  217. This function executes a Unprivileged LDRT instruction for 16 bit values.
  218. \param [in] ptr Pointer to data
  219. \return value of type uint16_t at (*ptr)
  220. */
  221. #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
  222. /** \brief LDRT Unprivileged (32 bit)
  223. This function executes a Unprivileged LDRT instruction for 32 bit values.
  224. \param [in] ptr Pointer to data
  225. \return value of type uint32_t at (*ptr)
  226. */
  227. #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
  228. /** \brief STRT Unprivileged (8 bit)
  229. This function executes a Unprivileged STRT instruction for 8 bit values.
  230. \param [in] value Value to store
  231. \param [in] ptr Pointer to location
  232. */
  233. #define __STRBT(value, ptr) __strt(value, ptr)
  234. /** \brief STRT Unprivileged (16 bit)
  235. This function executes a Unprivileged STRT instruction for 16 bit values.
  236. \param [in] value Value to store
  237. \param [in] ptr Pointer to location
  238. */
  239. #define __STRHT(value, ptr) __strt(value, ptr)
  240. /** \brief STRT Unprivileged (32 bit)
  241. This function executes a Unprivileged STRT instruction for 32 bit values.
  242. \param [in] value Value to store
  243. \param [in] ptr Pointer to location
  244. */
  245. #define __STRT(value, ptr) __strt(value, ptr)
  246. #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
  247. #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
  248. /* GNU gcc specific functions */
  249. /* Define macros for porting to both thumb1 and thumb2.
  250. * For thumb1, use low register (r0-r7), specified by constrant "l"
  251. * Otherwise, use general registers, specified by constrant "r" */
  252. #if defined (__thumb__) && !defined (__thumb2__)
  253. #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
  254. #define __CMSIS_GCC_USE_REG(r) "l" (r)
  255. #else
  256. #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
  257. #define __CMSIS_GCC_USE_REG(r) "r" (r)
  258. #endif
  259. /** \brief No Operation
  260. No Operation does nothing. This instruction can be used for code alignment purposes.
  261. */
  262. __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
  263. {
  264. __ASM volatile ("nop");
  265. }
  266. /** \brief Wait For Interrupt
  267. Wait For Interrupt is a hint instruction that suspends execution
  268. until one of a number of events occurs.
  269. */
  270. __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
  271. {
  272. __ASM volatile ("wfi");
  273. }
  274. /** \brief Wait For Event
  275. Wait For Event is a hint instruction that permits the processor to enter
  276. a low-power state until one of a number of events occurs.
  277. */
  278. __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
  279. {
  280. __ASM volatile ("wfe");
  281. }
  282. /** \brief Send Event
  283. Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  284. */
  285. __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
  286. {
  287. __ASM volatile ("sev");
  288. }
  289. /** \brief Instruction Synchronization Barrier
  290. Instruction Synchronization Barrier flushes the pipeline in the processor,
  291. so that all instructions following the ISB are fetched from cache or
  292. memory, after the instruction has been completed.
  293. */
  294. __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
  295. {
  296. __ASM volatile ("isb");
  297. }
  298. /** \brief Data Synchronization Barrier
  299. This function acts as a special kind of Data Memory Barrier.
  300. It completes when all explicit memory accesses before this instruction complete.
  301. */
  302. __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
  303. {
  304. __ASM volatile ("dsb");
  305. }
  306. /** \brief Data Memory Barrier
  307. This function ensures the apparent order of the explicit memory operations before
  308. and after the instruction, without ensuring their completion.
  309. */
  310. __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
  311. {
  312. __ASM volatile ("dmb");
  313. }
  314. /** \brief Reverse byte order (32 bit)
  315. This function reverses the byte order in integer value.
  316. \param [in] value Value to reverse
  317. \return Reversed value
  318. */
  319. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
  320. {
  321. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
  322. return __builtin_bswap32(value);
  323. #else
  324. uint32_t result;
  325. __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  326. return(result);
  327. #endif
  328. }
  329. /** \brief Reverse byte order (16 bit)
  330. This function reverses the byte order in two unsigned short values.
  331. \param [in] value Value to reverse
  332. \return Reversed value
  333. */
  334. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
  335. {
  336. uint32_t result;
  337. __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  338. return(result);
  339. }
  340. /** \brief Reverse byte order in signed short value
  341. This function reverses the byte order in a signed short value with sign extension to integer.
  342. \param [in] value Value to reverse
  343. \return Reversed value
  344. */
  345. __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
  346. {
  347. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  348. return (short)__builtin_bswap16(value);
  349. #else
  350. uint32_t result;
  351. __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  352. return(result);
  353. #endif
  354. }
  355. /** \brief Rotate Right in unsigned value (32 bit)
  356. This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  357. \param [in] value Value to rotate
  358. \param [in] value Number of Bits to rotate
  359. \return Rotated value
  360. */
  361. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
  362. {
  363. return (op1 >> op2) | (op1 << (32 - op2));
  364. }
  365. /** \brief Breakpoint
  366. This function causes the processor to enter Debug state.
  367. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  368. \param [in] value is ignored by the processor.
  369. If required, a debugger can use it to store additional information about the breakpoint.
  370. */
  371. #define __BKPT(value) __ASM volatile ("bkpt "#value)
  372. #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
  373. /** \brief Reverse bit order of value
  374. This function reverses the bit order of the given value.
  375. \param [in] value Value to reverse
  376. \return Reversed value
  377. */
  378. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  379. {
  380. uint32_t result;
  381. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  382. return(result);
  383. }
  384. /** \brief LDR Exclusive (8 bit)
  385. This function executes a exclusive LDR instruction for 8 bit value.
  386. \param [in] ptr Pointer to data
  387. \return value of type uint8_t at (*ptr)
  388. */
  389. __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
  390. {
  391. uint32_t result;
  392. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  393. __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
  394. #else
  395. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  396. accepted by assembler. So has to use following less efficient pattern.
  397. */
  398. __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  399. #endif
  400. return ((uint8_t) result); /* Add explicit type cast here */
  401. }
  402. /** \brief LDR Exclusive (16 bit)
  403. This function executes a exclusive LDR instruction for 16 bit values.
  404. \param [in] ptr Pointer to data
  405. \return value of type uint16_t at (*ptr)
  406. */
  407. __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
  408. {
  409. uint32_t result;
  410. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  411. __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
  412. #else
  413. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  414. accepted by assembler. So has to use following less efficient pattern.
  415. */
  416. __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  417. #endif
  418. return ((uint16_t) result); /* Add explicit type cast here */
  419. }
  420. /** \brief LDR Exclusive (32 bit)
  421. This function executes a exclusive LDR instruction for 32 bit values.
  422. \param [in] ptr Pointer to data
  423. \return value of type uint32_t at (*ptr)
  424. */
  425. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
  426. {
  427. uint32_t result;
  428. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  429. return(result);
  430. }
  431. /** \brief STR Exclusive (8 bit)
  432. This function executes a exclusive STR instruction for 8 bit values.
  433. \param [in] value Value to store
  434. \param [in] ptr Pointer to location
  435. \return 0 Function succeeded
  436. \return 1 Function failed
  437. */
  438. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
  439. {
  440. uint32_t result;
  441. __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
  442. return(result);
  443. }
  444. /** \brief STR Exclusive (16 bit)
  445. This function executes a exclusive STR instruction for 16 bit values.
  446. \param [in] value Value to store
  447. \param [in] ptr Pointer to location
  448. \return 0 Function succeeded
  449. \return 1 Function failed
  450. */
  451. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
  452. {
  453. uint32_t result;
  454. __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
  455. return(result);
  456. }
  457. /** \brief STR Exclusive (32 bit)
  458. This function executes a exclusive STR instruction for 32 bit values.
  459. \param [in] value Value to store
  460. \param [in] ptr Pointer to location
  461. \return 0 Function succeeded
  462. \return 1 Function failed
  463. */
  464. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
  465. {
  466. uint32_t result;
  467. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  468. return(result);
  469. }
  470. /** \brief Remove the exclusive lock
  471. This function removes the exclusive lock which is created by LDREX.
  472. */
  473. __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
  474. {
  475. __ASM volatile ("clrex" ::: "memory");
  476. }
  477. /** \brief Signed Saturate
  478. This function saturates a signed value.
  479. \param [in] value Value to be saturated
  480. \param [in] sat Bit position to saturate to (1..32)
  481. \return Saturated value
  482. */
  483. #define __SSAT(ARG1,ARG2) \
  484. ({ \
  485. uint32_t __RES, __ARG1 = (ARG1); \
  486. __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  487. __RES; \
  488. })
  489. /** \brief Unsigned Saturate
  490. This function saturates an unsigned value.
  491. \param [in] value Value to be saturated
  492. \param [in] sat Bit position to saturate to (0..31)
  493. \return Saturated value
  494. */
  495. #define __USAT(ARG1,ARG2) \
  496. ({ \
  497. uint32_t __RES, __ARG1 = (ARG1); \
  498. __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  499. __RES; \
  500. })
  501. /** \brief Count leading zeros
  502. This function counts the number of leading zeros of a data value.
  503. \param [in] value Value to count the leading zeros
  504. \return number of leading zeros in value
  505. */
  506. __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
  507. {
  508. uint32_t result;
  509. __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
  510. return ((uint8_t) result); /* Add explicit type cast here */
  511. }
  512. /** \brief Rotate Right with Extend (32 bit)
  513. This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
  514. \param [in] value Value to rotate
  515. \return Rotated value
  516. */
  517. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
  518. {
  519. uint32_t result;
  520. __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  521. return(result);
  522. }
  523. /** \brief LDRT Unprivileged (8 bit)
  524. This function executes a Unprivileged LDRT instruction for 8 bit value.
  525. \param [in] ptr Pointer to data
  526. \return value of type uint8_t at (*ptr)
  527. */
  528. __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
  529. {
  530. uint32_t result;
  531. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  532. __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
  533. #else
  534. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  535. accepted by assembler. So has to use following less efficient pattern.
  536. */
  537. __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  538. #endif
  539. return ((uint8_t) result); /* Add explicit type cast here */
  540. }
  541. /** \brief LDRT Unprivileged (16 bit)
  542. This function executes a Unprivileged LDRT instruction for 16 bit values.
  543. \param [in] ptr Pointer to data
  544. \return value of type uint16_t at (*ptr)
  545. */
  546. __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
  547. {
  548. uint32_t result;
  549. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  550. __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
  551. #else
  552. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  553. accepted by assembler. So has to use following less efficient pattern.
  554. */
  555. __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  556. #endif
  557. return ((uint16_t) result); /* Add explicit type cast here */
  558. }
  559. /** \brief LDRT Unprivileged (32 bit)
  560. This function executes a Unprivileged LDRT instruction for 32 bit values.
  561. \param [in] ptr Pointer to data
  562. \return value of type uint32_t at (*ptr)
  563. */
  564. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
  565. {
  566. uint32_t result;
  567. __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
  568. return(result);
  569. }
  570. /** \brief STRT Unprivileged (8 bit)
  571. This function executes a Unprivileged STRT instruction for 8 bit values.
  572. \param [in] value Value to store
  573. \param [in] ptr Pointer to location
  574. */
  575. __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
  576. {
  577. __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
  578. }
  579. /** \brief STRT Unprivileged (16 bit)
  580. This function executes a Unprivileged STRT instruction for 16 bit values.
  581. \param [in] value Value to store
  582. \param [in] ptr Pointer to location
  583. */
  584. __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
  585. {
  586. __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
  587. }
  588. /** \brief STRT Unprivileged (32 bit)
  589. This function executes a Unprivileged STRT instruction for 32 bit values.
  590. \param [in] value Value to store
  591. \param [in] ptr Pointer to location
  592. */
  593. __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
  594. {
  595. __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
  596. }
  597. #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
  598. #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
  599. /* IAR iccarm specific functions */
  600. #include <cmsis_iar.h>
  601. #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
  602. /* TI CCS specific functions */
  603. #include <cmsis_ccs.h>
  604. #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
  605. /* TASKING carm specific functions */
  606. /*
  607. * The CMSIS functions have been implemented as intrinsics in the compiler.
  608. * Please use "carm -?i" to get an up to date list of all intrinsics,
  609. * Including the CMSIS ones.
  610. */
  611. #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
  612. /* Cosmic specific functions */
  613. #include <cmsis_csm.h>
  614. #endif
  615. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
  616. #endif /* __CORE_CMINSTR_H */