stm32f4xx_fsmc.h 26 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_fsmc.h
  4. * @author MCD Application Team
  5. * @version V1.5.0
  6. * @date 06-March-2015
  7. * @brief This file contains all the functions prototypes for the FSMC firmware
  8. * library.
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
  13. *
  14. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  15. * You may not use this file except in compliance with the License.
  16. * You may obtain a copy of the License at:
  17. *
  18. * http://www.st.com/software_license_agreement_liberty_v2
  19. *
  20. * Unless required by applicable law or agreed to in writing, software
  21. * distributed under the License is distributed on an "AS IS" BASIS,
  22. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  23. * See the License for the specific language governing permissions and
  24. * limitations under the License.
  25. *
  26. ******************************************************************************
  27. */
  28. /* Define to prevent recursive inclusion -------------------------------------*/
  29. #ifndef __STM32F4xx_FSMC_H
  30. #define __STM32F4xx_FSMC_H
  31. #ifdef __cplusplus
  32. extern "C" {
  33. #endif
  34. /* Includes ------------------------------------------------------------------*/
  35. #include "stm32f4xx.h"
  36. /** @addtogroup STM32F4xx_StdPeriph_Driver
  37. * @{
  38. */
  39. /** @addtogroup FSMC
  40. * @{
  41. */
  42. /* Exported types ------------------------------------------------------------*/
  43. /**
  44. * @brief Timing parameters For NOR/SRAM Banks
  45. */
  46. typedef struct
  47. {
  48. uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
  49. the duration of the address setup time.
  50. This parameter can be a value between 0 and 0xF.
  51. @note This parameter is not used with synchronous NOR Flash memories. */
  52. uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
  53. the duration of the address hold time.
  54. This parameter can be a value between 0 and 0xF.
  55. @note This parameter is not used with synchronous NOR Flash memories.*/
  56. uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
  57. the duration of the data setup time.
  58. This parameter can be a value between 0 and 0xFF.
  59. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
  60. uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
  61. the duration of the bus turnaround.
  62. This parameter can be a value between 0 and 0xF.
  63. @note This parameter is only used for multiplexed NOR Flash memories. */
  64. uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
  65. This parameter can be a value between 1 and 0xF.
  66. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
  67. uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
  68. to the memory before getting the first data.
  69. The parameter value depends on the memory type as shown below:
  70. - It must be set to 0 in case of a CRAM
  71. - It is don't care in asynchronous NOR, SRAM or ROM accesses
  72. - It may assume a value between 0 and 0xF in NOR Flash memories
  73. with synchronous burst mode enable */
  74. uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
  75. This parameter can be a value of @ref FSMC_Access_Mode */
  76. }FSMC_NORSRAMTimingInitTypeDef;
  77. /**
  78. * @brief FSMC NOR/SRAM Init structure definition
  79. */
  80. typedef struct
  81. {
  82. uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
  83. This parameter can be a value of @ref FSMC_NORSRAM_Bank */
  84. uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
  85. multiplexed on the data bus or not.
  86. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
  87. uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
  88. the corresponding memory bank.
  89. This parameter can be a value of @ref FSMC_Memory_Type */
  90. uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
  91. This parameter can be a value of @ref FSMC_Data_Width */
  92. uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
  93. valid only with synchronous burst Flash memories.
  94. This parameter can be a value of @ref FSMC_Burst_Access_Mode */
  95. uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
  96. valid only with asynchronous Flash memories.
  97. This parameter can be a value of @ref FSMC_AsynchronousWait */
  98. uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
  99. the Flash memory in burst mode.
  100. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
  101. uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
  102. memory, valid only when accessing Flash memories in burst mode.
  103. This parameter can be a value of @ref FSMC_Wrap_Mode */
  104. uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
  105. clock cycle before the wait state or during the wait state,
  106. valid only when accessing memories in burst mode.
  107. This parameter can be a value of @ref FSMC_Wait_Timing */
  108. uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
  109. This parameter can be a value of @ref FSMC_Write_Operation */
  110. uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
  111. signal, valid for Flash memory access in burst mode.
  112. This parameter can be a value of @ref FSMC_Wait_Signal */
  113. uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
  114. This parameter can be a value of @ref FSMC_Extended_Mode */
  115. uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
  116. This parameter can be a value of @ref FSMC_Write_Burst */
  117. FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
  118. FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
  119. }FSMC_NORSRAMInitTypeDef;
  120. /**
  121. * @brief Timing parameters For FSMC NAND and PCCARD Banks
  122. */
  123. typedef struct
  124. {
  125. uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
  126. the command assertion for NAND Flash read or write access
  127. to common/Attribute or I/O memory space (depending on
  128. the memory space timing to be configured).
  129. This parameter can be a value between 0 and 0xFF.*/
  130. uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
  131. command for NAND Flash read or write access to
  132. common/Attribute or I/O memory space (depending on the
  133. memory space timing to be configured).
  134. This parameter can be a number between 0x00 and 0xFF */
  135. uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
  136. (and data for write access) after the command de-assertion
  137. for NAND Flash read or write access to common/Attribute
  138. or I/O memory space (depending on the memory space timing
  139. to be configured).
  140. This parameter can be a number between 0x00 and 0xFF */
  141. uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
  142. data bus is kept in HiZ after the start of a NAND Flash
  143. write access to common/Attribute or I/O memory space (depending
  144. on the memory space timing to be configured).
  145. This parameter can be a number between 0x00 and 0xFF */
  146. }FSMC_NAND_PCCARDTimingInitTypeDef;
  147. /**
  148. * @brief FSMC NAND Init structure definition
  149. */
  150. typedef struct
  151. {
  152. uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
  153. This parameter can be a value of @ref FSMC_NAND_Bank */
  154. uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
  155. This parameter can be any value of @ref FSMC_Wait_feature */
  156. uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
  157. This parameter can be any value of @ref FSMC_Data_Width */
  158. uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
  159. This parameter can be any value of @ref FSMC_ECC */
  160. uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
  161. This parameter can be any value of @ref FSMC_ECC_Page_Size */
  162. uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
  163. delay between CLE low and RE low.
  164. This parameter can be a value between 0 and 0xFF. */
  165. uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
  166. delay between ALE low and RE low.
  167. This parameter can be a number between 0x0 and 0xFF */
  168. FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
  169. FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
  170. }FSMC_NANDInitTypeDef;
  171. /**
  172. * @brief FSMC PCCARD Init structure definition
  173. */
  174. typedef struct
  175. {
  176. uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
  177. This parameter can be any value of @ref FSMC_Wait_feature */
  178. uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
  179. delay between CLE low and RE low.
  180. This parameter can be a value between 0 and 0xFF. */
  181. uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
  182. delay between ALE low and RE low.
  183. This parameter can be a number between 0x0 and 0xFF */
  184. FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
  185. FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
  186. FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
  187. }FSMC_PCCARDInitTypeDef;
  188. /* Exported constants --------------------------------------------------------*/
  189. /** @defgroup FSMC_Exported_Constants
  190. * @{
  191. */
  192. /** @defgroup FSMC_NORSRAM_Bank
  193. * @{
  194. */
  195. #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
  196. #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
  197. #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
  198. #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
  199. /**
  200. * @}
  201. */
  202. /** @defgroup FSMC_NAND_Bank
  203. * @{
  204. */
  205. #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
  206. #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
  207. /**
  208. * @}
  209. */
  210. /** @defgroup FSMC_PCCARD_Bank
  211. * @{
  212. */
  213. #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
  214. /**
  215. * @}
  216. */
  217. #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
  218. ((BANK) == FSMC_Bank1_NORSRAM2) || \
  219. ((BANK) == FSMC_Bank1_NORSRAM3) || \
  220. ((BANK) == FSMC_Bank1_NORSRAM4))
  221. #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
  222. ((BANK) == FSMC_Bank3_NAND))
  223. #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
  224. ((BANK) == FSMC_Bank3_NAND) || \
  225. ((BANK) == FSMC_Bank4_PCCARD))
  226. #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
  227. ((BANK) == FSMC_Bank3_NAND) || \
  228. ((BANK) == FSMC_Bank4_PCCARD))
  229. /** @defgroup FSMC_NOR_SRAM_Controller
  230. * @{
  231. */
  232. /** @defgroup FSMC_Data_Address_Bus_Multiplexing
  233. * @{
  234. */
  235. #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
  236. #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
  237. #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
  238. ((MUX) == FSMC_DataAddressMux_Enable))
  239. /**
  240. * @}
  241. */
  242. /** @defgroup FSMC_Memory_Type
  243. * @{
  244. */
  245. #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
  246. #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
  247. #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
  248. #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
  249. ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
  250. ((MEMORY) == FSMC_MemoryType_NOR))
  251. /**
  252. * @}
  253. */
  254. /** @defgroup FSMC_Data_Width
  255. * @{
  256. */
  257. #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
  258. #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
  259. #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
  260. ((WIDTH) == FSMC_MemoryDataWidth_16b))
  261. /**
  262. * @}
  263. */
  264. /** @defgroup FSMC_Burst_Access_Mode
  265. * @{
  266. */
  267. #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
  268. #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
  269. #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
  270. ((STATE) == FSMC_BurstAccessMode_Enable))
  271. /**
  272. * @}
  273. */
  274. /** @defgroup FSMC_AsynchronousWait
  275. * @{
  276. */
  277. #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
  278. #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
  279. #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
  280. ((STATE) == FSMC_AsynchronousWait_Enable))
  281. /**
  282. * @}
  283. */
  284. /** @defgroup FSMC_Wait_Signal_Polarity
  285. * @{
  286. */
  287. #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
  288. #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
  289. #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
  290. ((POLARITY) == FSMC_WaitSignalPolarity_High))
  291. /**
  292. * @}
  293. */
  294. /** @defgroup FSMC_Wrap_Mode
  295. * @{
  296. */
  297. #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
  298. #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
  299. #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
  300. ((MODE) == FSMC_WrapMode_Enable))
  301. /**
  302. * @}
  303. */
  304. /** @defgroup FSMC_Wait_Timing
  305. * @{
  306. */
  307. #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
  308. #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
  309. #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
  310. ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
  311. /**
  312. * @}
  313. */
  314. /** @defgroup FSMC_Write_Operation
  315. * @{
  316. */
  317. #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
  318. #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
  319. #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
  320. ((OPERATION) == FSMC_WriteOperation_Enable))
  321. /**
  322. * @}
  323. */
  324. /** @defgroup FSMC_Wait_Signal
  325. * @{
  326. */
  327. #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
  328. #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
  329. #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
  330. ((SIGNAL) == FSMC_WaitSignal_Enable))
  331. /**
  332. * @}
  333. */
  334. /** @defgroup FSMC_Extended_Mode
  335. * @{
  336. */
  337. #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
  338. #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
  339. #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
  340. ((MODE) == FSMC_ExtendedMode_Enable))
  341. /**
  342. * @}
  343. */
  344. /** @defgroup FSMC_Write_Burst
  345. * @{
  346. */
  347. #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
  348. #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
  349. #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
  350. ((BURST) == FSMC_WriteBurst_Enable))
  351. /**
  352. * @}
  353. */
  354. /** @defgroup FSMC_Address_Setup_Time
  355. * @{
  356. */
  357. #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
  358. /**
  359. * @}
  360. */
  361. /** @defgroup FSMC_Address_Hold_Time
  362. * @{
  363. */
  364. #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
  365. /**
  366. * @}
  367. */
  368. /** @defgroup FSMC_Data_Setup_Time
  369. * @{
  370. */
  371. #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
  372. /**
  373. * @}
  374. */
  375. /** @defgroup FSMC_Bus_Turn_around_Duration
  376. * @{
  377. */
  378. #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
  379. /**
  380. * @}
  381. */
  382. /** @defgroup FSMC_CLK_Division
  383. * @{
  384. */
  385. #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
  386. /**
  387. * @}
  388. */
  389. /** @defgroup FSMC_Data_Latency
  390. * @{
  391. */
  392. #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
  393. /**
  394. * @}
  395. */
  396. /** @defgroup FSMC_Access_Mode
  397. * @{
  398. */
  399. #define FSMC_AccessMode_A ((uint32_t)0x00000000)
  400. #define FSMC_AccessMode_B ((uint32_t)0x10000000)
  401. #define FSMC_AccessMode_C ((uint32_t)0x20000000)
  402. #define FSMC_AccessMode_D ((uint32_t)0x30000000)
  403. #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
  404. ((MODE) == FSMC_AccessMode_B) || \
  405. ((MODE) == FSMC_AccessMode_C) || \
  406. ((MODE) == FSMC_AccessMode_D))
  407. /**
  408. * @}
  409. */
  410. /**
  411. * @}
  412. */
  413. /** @defgroup FSMC_NAND_PCCARD_Controller
  414. * @{
  415. */
  416. /** @defgroup FSMC_Wait_feature
  417. * @{
  418. */
  419. #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
  420. #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
  421. #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
  422. ((FEATURE) == FSMC_Waitfeature_Enable))
  423. /**
  424. * @}
  425. */
  426. /** @defgroup FSMC_ECC
  427. * @{
  428. */
  429. #define FSMC_ECC_Disable ((uint32_t)0x00000000)
  430. #define FSMC_ECC_Enable ((uint32_t)0x00000040)
  431. #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
  432. ((STATE) == FSMC_ECC_Enable))
  433. /**
  434. * @}
  435. */
  436. /** @defgroup FSMC_ECC_Page_Size
  437. * @{
  438. */
  439. #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
  440. #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
  441. #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
  442. #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
  443. #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
  444. #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
  445. #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
  446. ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
  447. ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
  448. ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
  449. ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
  450. ((SIZE) == FSMC_ECCPageSize_8192Bytes))
  451. /**
  452. * @}
  453. */
  454. /** @defgroup FSMC_TCLR_Setup_Time
  455. * @{
  456. */
  457. #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
  458. /**
  459. * @}
  460. */
  461. /** @defgroup FSMC_TAR_Setup_Time
  462. * @{
  463. */
  464. #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
  465. /**
  466. * @}
  467. */
  468. /** @defgroup FSMC_Setup_Time
  469. * @{
  470. */
  471. #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
  472. /**
  473. * @}
  474. */
  475. /** @defgroup FSMC_Wait_Setup_Time
  476. * @{
  477. */
  478. #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
  479. /**
  480. * @}
  481. */
  482. /** @defgroup FSMC_Hold_Setup_Time
  483. * @{
  484. */
  485. #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
  486. /**
  487. * @}
  488. */
  489. /** @defgroup FSMC_HiZ_Setup_Time
  490. * @{
  491. */
  492. #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
  493. /**
  494. * @}
  495. */
  496. /** @defgroup FSMC_Interrupt_sources
  497. * @{
  498. */
  499. #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
  500. #define FSMC_IT_Level ((uint32_t)0x00000010)
  501. #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
  502. #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
  503. #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
  504. ((IT) == FSMC_IT_Level) || \
  505. ((IT) == FSMC_IT_FallingEdge))
  506. /**
  507. * @}
  508. */
  509. /** @defgroup FSMC_Flags
  510. * @{
  511. */
  512. #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
  513. #define FSMC_FLAG_Level ((uint32_t)0x00000002)
  514. #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
  515. #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
  516. #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
  517. ((FLAG) == FSMC_FLAG_Level) || \
  518. ((FLAG) == FSMC_FLAG_FallingEdge) || \
  519. ((FLAG) == FSMC_FLAG_FEMPT))
  520. #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
  521. /**
  522. * @}
  523. */
  524. /**
  525. * @}
  526. */
  527. /**
  528. * @}
  529. */
  530. /* Exported macro ------------------------------------------------------------*/
  531. /* Exported functions --------------------------------------------------------*/
  532. /* NOR/SRAM Controller functions **********************************************/
  533. void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
  534. void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
  535. void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
  536. void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
  537. /* NAND Controller functions **************************************************/
  538. void FSMC_NANDDeInit(uint32_t FSMC_Bank);
  539. void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
  540. void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
  541. void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
  542. void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
  543. uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
  544. /* PCCARD Controller functions ************************************************/
  545. void FSMC_PCCARDDeInit(void);
  546. void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
  547. void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
  548. void FSMC_PCCARDCmd(FunctionalState NewState);
  549. /* Interrupts and flags management functions **********************************/
  550. void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
  551. FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
  552. void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
  553. ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
  554. void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
  555. #ifdef __cplusplus
  556. }
  557. #endif
  558. #endif /*__STM32F4xx_FSMC_H */
  559. /**
  560. * @}
  561. */
  562. /**
  563. * @}
  564. */
  565. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/